PSoC 6 Serial Communication Blocks (SCBs)

[Anonymous]

Hello!

Thought I'd introduce the Serial Communication Blocks (SCBs) in the PSoC 6 architecture. Our first PSoC 6 lineup, the PSoC 63 Connectivity lineup has nine SCBs. Each SCB can be configured for either I2C, SPI, or UART. The mode of operation of the SCB can be changed during run time. The PSoC 6 SCBs have two 128 byte deep FIFOs, one for transmit and one for receive. These FIFOs can be written/read by both the CPU and DMA. One of the SCBs out of the nine in PSoC 6 is designed to wake the device up from deep-sleep modes of operation, this SCB is called the deep-sleep SCB. This wakeup can occur on I2C address match, or SPI slave select assertion.

Feel free to leave comments or ask questions, we appreciate the feedback!

[cadi_1014291]

128 bytes deep FIFO is a lot bigger than the P4 SCB blocks , that FIFOs are hardware or software implemented?

PD: When can we expect the TRM or at least some data sheets of the P6 family?

[Anonymous]

Hello,

Appreciate the question, the FIFOs are hardware-based. As for documentation, such as the TRM and datasheets, we will post them in the coming weeks. Datasheet first, in the next 2-3 weeks, then the TRMs after.

Thanks!

[cadi_1014291]

Thanks for the reply iym, i guess we can expect Creator 4.1 on the same time frame?.

[Anonymous]

Hello, Creator 4.1 is planned for release next week, stay tuned!

[user_300221]

Hello,

How many databits can be configured in SCB?

For example Infineon's MCUs have USICs. It can by configured for 1 to 63 bits data frame at UART or SPI mode. That's too mach. However 9 bit UART and 16 bit SPI would by useful.

[AchimE_41]

Hello, SCBs can be configured from 5 to 9bit in UART mode and 4 to 16bit in SPI mode.

[Anonymous]

Hello, what would be maximum frequency that SPI can run at?

[Anonymous]

Hello,

The current spec for maximum frequency that SPI runs at is 25MHz. Is this spec enough for you or you are looking for something better?

Thanks!

[Anonymous]

Hi,

Yes, I am trying to get SPI run at 45-50 MHz without using FPGA.

[AchimE_41]

HI,

What type of device will be connected to the SPI in your application?

[Anonymous]

A custom ASIC.

[AchimE_41]

The Serial Memory Interface (SMIF) of PSoC6 might be something for your.

It is a Single-, Dual-, Quad- and Octal SPI interface surpassing your required frequency.

Unfortunately the only unveiled snipped is currently in the PSoC 6 BLE Hardware Design Considerations_Full_Draft (page 22) so I think I am not allowed to tell you more . But an introduction to the SMIF is planned as well for the upcoming week/s.

stay tuned.

[Anonymous]

Mapping our ASIC into memory space sounds very interesting. Thank you.

[Anonymous]

I can only ever add 8 of 9 SCBs before analog routing fails.  any clues?

PSoC Creator 4.2

CY8CKIT-062-BLE

[AchimE_41]

Jason,

One of the 9 SCBs is Slave only. This one is capable to run in DeepSleep with external clock.