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PSoC 6 Flash

Anonymous
Not applicable

PSoC 6 Flash

Hello,

Thought I'd give an introduction on the flash in the PSoC 6 architecture.

Our first PSoC 6 device has up to 1MB of flash. A flash controller does 128-bit wide flash reads, to reduce power. PSoC 6 flash has read-while-write (RWW) capability, which allows updating the flash while executing from it. This is useful for applications that update flash, such as bootloaders and data loggers. The CPUs in PSoC 6 each have an 8KB 4-way set-associative flash cache. This reduces the number of flash accesses for CPU instructions, which in turn increases CPU execution speed and reduces power. The CPU subsystem architecture incorporates multiple bus masters – the two CPU cores as well as two DMA controllers and a cryptography block (Crypto). Generally, all memory and peripherals are shared by all of the bus masters. Shared resources are accessed through standard ARM multi-layer bus arbitration. Exclusive accesses are supported by an inter-processor communication (IPC) block, which implements hardware semaphores and mutual exclusion (mutexes).

Feel free to leave comments and questions, we appreciate the feedback!

Comments
Anonymous
Not applicable

Whether Bootloader will be embedded in  to ROM, to facilitate the subsequent upgrade?

MarkA_91
Employee

Hi Helon,

A bootloader is not embedded in the PSoC 6 ROM. Instead, the PDL has a Bootloader software development kit (SDK). You can use this SDK to quickly and easily develop custom bootloader systems with a variety of features to meet your application requirements. An application note guide and code examples will be published soon.

Anonymous
Not applicable

Hi mkea,

    Thanks for your reply.I get it,Hope that application note guide and code examples can be released as soon as possible

Anonymous
Not applicable

Hello,

When we want to write user data into Flash, although we can write it in NMI in M0+ core, cannot we write it from use application of M4 or M0+ core directly?

Best regards,

MeenakshiR_71
Employee

You can - all you need to do is call the appropriate APIs provided with the Flash driver PDL. Depending on the core that is calling the API, it automatically decides how the flash write/erase calls are initiated.

That said, the flash write/erase still happens through M0+'s NMI handler only. All the requests are ultimately sent to this handler through the API.

baba_1710186
New Contributor

Hi,

How much are the current consumption for erase and program of the flash/eeprom (row, sector, bulk) ?

Thanks,

BB

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‎Apr 11, 2017 04:01 PM
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Anonymous
 
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