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Thought I'd give an introduction on the flash in the PSoC 6 architecture.
Our first PSoC 6 device has up to 1MB of flash. A flash controller does 128-bit wide flash reads, to reduce power. PSoC 6 flash has read-while-write (RWW) capability, which allows updating the flash while executing from it. This is useful for applications that update flash, such as bootloaders and data loggers. The CPUs in PSoC 6 each have an 8KB 4-way set-associative flash cache. This reduces the number of flash accesses for CPU instructions, which in turn increases CPU execution speed and reduces power. The CPU subsystem architecture incorporates multiple bus masters – the two CPU cores as well as two DMA controllers and a cryptography block (Crypto). Generally, all memory and peripherals are shared by all of the bus masters. Shared resources are accessed through standard ARM multi-layer bus arbitration. Exclusive accesses are supported by an inter-processor communication (IPC) block, which implements hardware semaphores and mutual exclusion (mutexes).
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