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MDIO Interface Component for PSoC 6


MDIO Interface Component for PSoC 6

The attached document contains a project based on AN83902 that contains the implementation of the MDIO Interface component for PSoC 6.

New Contributor II

Hi RodolfoG_11

Can you please provide details on how was this component tested, which PHY device and the interfacing circuitry?





We have internally tested using our own tools/hardware. Both sides (Host and Slave) were Cypress implementation to confirm that the MDIO interface spec was followed.

However, we already have many customers using this component, which was validated using PHY devices.

New Contributor II

hi Rodolfo,

I am one of your Cypress sales reps.  I have a customer that wants to use PSOC6 in a CFP like module.  Could you please confirm that AN83902 contains the PSOC6 implementation for host & slave MDIO interface?  Also, would you use Modus toolbox or creator to implement? Thanks!


Hi John,

The AN83902 has the implementation of the Host and Slave MDIO Interface for PSoC 6, but only in Basic mode. Ideally, you want to use PSoC Creator, however, there are some hooks we can do to work with ModusToolbox. The component uses UDBs, so you have to use the PSoC 6-1M family.

New Contributor

Hi Rodolfo,

Do you have plans to implement the advance mode as well?

Also, can you please explain the hooks required to work make this work with ModusToolbox?




Hi Suresh,

Yes, we are in discussion to implement the MDIO Advance Mode in PSoC 6.

I see two ways to do this:

1) Use the steps provided in this blog:

2) Or we can create a library to wrap the UDB configuration, as we did for the SDIO driver for ModusToolbox.

GitHub - cypresssemiconductorco/udb-sdio-whd: UDB based SDIO support for Wi-Fi Host Driver

New Contributor

Hello Rodolfo,

Thanks for your links.

New Contributor

Hello Rodolfo,

When I try to port this project using UDB porting tool (@oneThinx), I see I get only the PhyAddr_CtrlReg component getting ported and the MDIO interface, host, UART do not get ported. Did I miss anything here? Please guide me if this is not the right forum to discuss UDB porting issues.

Below is the OneThinx log:

Project Loaded: Example1_P6

The following components are found:

- PhyAddr_CtrlReg

Start parsing cyfitter_cfg.c at 12-11-2020 17:19:44

Changed line 2 to: * File Name: UDBfitter.c

Changed line 9 to: * This file was automatically generated by PSoC Creator and is ported for universal use by a Onethinx Tool (c).

Found ClockInit() at line 188, skipping code...

Found peripheral clock setting at line 253, adding code...

Found Cy_SystemInit() at line 309, changed function name and skipping code...

Found clock setting at line 328, adding code...

Parsing succeedded, total time: 31 mS

Updating PDL references in cyfitter_cfg.c at 12-11-2020 17:19:44

Changed header folder structure at line 21 for new PDL.

Changed header folder structure at line 22 for new PDL.

Changed header folder structure at line 25 for new PDL.

Changed header folder structure at line 26 for new PDL.

Changed header folder structure at line 29 for new PDL.

Updating succeedded, total time: 47 mS




The UART in the does not use UDBs. It uses the fixed function SCB block.

Version history
Revision #:
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Last update:
‎May 24, 2018 02:04 PM
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