CYW20719 and CYW20735 have multiple clock dividers and PLLs routed to several high-speed and low-speed peripherals. There are basically two types of clocks on the device: high-frequency and low-frequency clock sources.
High-frequency clock sources:
This clock is derived from an external 24 MHz crystal oscillator using internal PLLs to upscale the frequency.
Low frequency clock sources:
There are three lean high land (LHL) low power oscillators (LPOs) available. They are LP-LPO (32 kHz), HP-LPO (32 kHz), and XTAL32K (32 kHz). The firmware decides which clock source to use among the available LPOs depending on the accuracy and power requirements. It is recommended to use an external 32.768 kHz crystal oscillator with low error PPM to improve the clock accuracy and lower average current consumption in Sleep, Power Down Sleep (PDS), or Shut-Down Sleep (SDS) mode. The firmware assumes the external LPO has lower (less than 250 PPM) error with little or no jitter.
The CYW20719 and CYW20735 supports a 48-bit RTC timer running on the 32-kHz crystal (XTAL32K) LPO. If an external LPO is not connected to CYW20719, then the firmware takes the clock input from the internal LPO for the RTC. WICED Studio provides APIs to set the current time, get the current time, or convert the current time value to a string. By default, the date and time are set to January 1, 2010 with a time of 00:00:00 denoting HH: MM: SS. It is mandatory to set the oscillator frequency to 32 kHz with the provided APIs when a 32-kHz external LPO is used. The RTC configuration structure (RTCconfig) has two member variables oscillatorFrequencykHz and rtcRefClock whose values must be set to RTC_REF_CLOCK_SRC_32KHZ.
The Watchdog module in CYW20719 and CYW20735 is based on a 32-bit down counter that is used to detect and recover from malfunctions. During normal operation, the device regularly resets the watchdog timer before the count value reaches zero to prevent it from elapsing, or “timing out”. If, due to a hardware fault or program error, the device fails to reset the watchdog, the timer will elapse and generate a system reset on time out. The process of restarting the watchdog timer’s counter is referred to as “kicking or petting the dog”.
WICED Studio provides limited debugging functionalities via the watchdog timer. The default watchdog timeout is set to 2 seconds and watchdog petting is done in the idle thread. Production applications need not pet the watchdog. When the watchdog expires, the system will reset after a core-dump. The core-dump contains the following information: device firmware or hardware version, warning-flag, memory info, CPU/HW registers, SRAM, and Patch RAM image. The core dump is sent over the HCI-UART as BT-HCI vendor specific events.
CYW20719 and CYW20735 provides one general-purpose 32 bit dual-input timer. The firmware uses the 2 x 32-bit timers as a 1 x 64-bit timer. WICED Studio provides APIs to use the timer functionality. The timer supports two modes of operation:
The WICED API provides four timer types:
The two periodic timers mentioned above are triggered every time the timer count reaches zero whereas the other two timers are single-shot.
The wiced_init_timer() API initializes the timer. It allows you to specify the callback function to be invoked when the timer expires. This API also allows you to specify timer type that should be used. This API does not start the timer.
The wiced_start_timer() API is used to start the count down. The wiced_stop_timer() API can be used to stop the timer.
The wiced_is_timer_in_use() function allows you to know if the specified timer is currently in use by returning a Boolean value.
There are six 16-bit Hardware PWM channels available in CYW20719 and CYW20735. The PWM of CYW20719 and CYW20735 is not glitch-free. The clock frequency of each PWM can be configured in one of the two ways. The LHL_CLK or PMU_CLK can be used as the clock source for the PWM. If the clock source is the LHL_CLK, then the clock frequency will be 32 kHz or 128 kHz based on the LHL clock priority. The PMU_CLK requires the auxiliary clock to be configured first. When configuring the auxiliary clock, ACLK0 is not available for use with the PWMs. Hence, ACLK1 is the only available PMU_CLK running at 24 MHz or at 1MHz using internal clock division. The wiced_hal_aclk_enable() function in wiced_hal_aclk.h enables the auxiliary clock and allows the functionality of choosing either 1 MHz or 24 MHz for routing to the PWMs.
The wiced_hal_pwm_start() function configures, enables, and starts the PWM and also routes it to a preconfigured GPIO pin. The desired GPIO pin must be configured as an output before configuring it for use with a PWM. Each PWM channel can be routed to GPIO pins using the SuperMUX. See the datasheet for more details. This function takes in 5 parameters (i.e., channel, clock source, toggle count, initial count and invert signal). The channel refers to PWM channels 0 to 5. The clock source can be either LHL_CLK or ACLK1 (PMU_CLK). The toggle count refers to the number of ticks to wait before toggling the signal. The initial count is the initial value of the register. The invert signal can be either 1 or 0. If the invert signal is 1, the PWM output starts HIGH and if the invert signal is 0, the PWM output starts LOW.
The wiced_hal_pwm_change_values() function changes the PWM settings such as toggle count and initial count of a specific PWM channel after the PWM hardware block has already been started.
The wiced_hal_pwm_configure_pin() function can be used to map any LHL GPIO to the specified PWM channel.
The wiced_hal_pwm_get_params() is a helper function that calculates the PWM parameters. This function takes in three parameters: input clock frequency, duty cycle, and desired PWM output frequency to determine the required initial count and toggle count. The initial count and toggle count is determined by the API using the following expression:
Initial count = 0xFFFF - (Input Clock Freq / PWM Freq out)
Toggle count = 0xFFFF - ((duty cycle in percentage) * (Input Clock Freq / PWM Freq out) / 100)