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CONFIG CCGx FIRMWARE FOR DISPLAYPORT SOURCE AND SINK ROLE CHANGE

CONFIG CCGx FIRMWARE FOR DISPLAYPORT SOURCE AND SINK ROLE CHANGE

ShifangZ_26
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Cypress SDK firmware demonstrate below feature in difference SDK firmware (@ December, 2018).

1. CCGx Host SDK (http://www.cypress.com/documentation/software-and-drivers/ez-pd-software-development-kit?source=sear...  )

>> Power Source and Sink Role;

>> DisplayPort Source Role with Alternate Mode.

 

2. CCGx Power SDK (http://www.cypress.com/documentation/software-and-drivers/ez-pd-ccgx-power-software-development-kit?... )

>> Power Source and Sink Role;

 

3. CCGx Dock SDK (http://www.cypress.com/documentation/reference-designs/ez-pd-ccg4-usb-type-c-monitordock-solution  )

>> Power Source and Sink Role;

>> DisplayPort Sink Role with Alternate Mode.

 

If you want to change DisplayPort Role based on above #1 and #3, either DisplayPort Source to DisplayPort Sink or DisplayPort Sink to DisplayPort Source. Only need take attention on below define to make sure below defines have been configured as per design requirements.

 

For Example: DisplayPort Source based Projects change to DisplayPort Sink.

@file: config.h

DISABLE OR REMOVE/COMMENT OUT

/* Enable Alternate Mode support when CCG is DFP. */

#define DFP_ALT_MODE_SUPP                           (0u)

 

 

/* Enable DisplayPort Source support as DFP. */

#define DP_DFP_SUPP                                 (0u)

 

ENABLE OR ADD IN

/* Enable Alternate mode support as UFP. */

#define UFP_ALT_MODE_SUPP                           (1u)

 

 

/* Enable DP Alternate mode support in UFP mode. */

#define DP_UFP_SUPP                                 (1u)

 

@file: alt_modes_config.h

DISABLE OR REMOVE/COMMENT OUT

#define DFP_MAX_SVID_SUPP                       (0u)

 

ENABLE OR ADD IN

#define UFP_MAX_SVID_SUPP                       (1u)

 

#define MAX_SVID_SUPP                           (DFP_MAX_SVID_SUPP > UFP_MAX_SVID_SUPP ? \

                                                        DFP_MAX_SVID_SUPP : UFP_MAX_SVID_SUPP)

 

@Software: EZ-PD configuration Utility

a. Open Ez-PD configuration Utilities to add SVID of DisplayPort Sink.

b. Select SVID Configuration and click +Add, SVID 0 will be add under SVID Configuration.

c. Select SVID 0 and edit SVID value and Mode on the right page. Change SVID value 0x0000 (default) to 0xFF01, Mode 0 value from 0x0 to 0x00001405(Plug design)/0x00040045(receptacle design).

d. Click File>Save As.

e. Find the .c file under the folder you have been saved on step c) above.

pastedImage_3.png

f. Open config.c under Source files in project. Change config table const unsigned char __attribute__ ((section (".configSection"), used)) gl_config_table[0x0400] by replace the table value from the .c file from Ez-PD configure Utilities above.

 

Otherwise, DisplayPort Sink change to DisplayPort Source is revise above ENABLE and DISABLE items.

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Flance_Fang
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Hi.Lisa

该功能学习了一下,非常明白DisplayPort Source based Projects change to DisplayPort Sink的过程,不过按照你提示,我用官方的CYPD4125-40LQXI_notebook(C:\Program Files (x86)\Cypress\EZ-PD CCGx SDK\CCG3-CCG4\Firmware\projects) 进行修改编译了一下: 发现如果设置了#define DP_UFP_SUPP       (1u)话,编译提示3个没有定义,!is_hpd_rx_state_idle (port)hpd_rx_sleep_entry (port, dp_snk_get_hpd_state(port))hpd_rx_wakeup (port);只能恢复设置0u;另外要修改dfp_compatibility_mode_table和DFP_MAX_SVID_SUPP变成下面这句才能编译通过。

ufp_compatibility_mode_table[(UFP_MAX_SVID_SUPP)][(UFP_MAX_SVID_SUPP)] =

{

    {{DP_SVID, DP_ALT_MODE_ID}},        /* Use DisplayPort SVID and Alt. Mode index 0. */

};

thank

flance fang