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We are using the fine pitch (WLCSP131) version of the CYUSB3014 on a custom board. The design is bus powered and using USB boot and an 19.2 MHz crystal with PMODE and FSEL configured accordingly.
At power up the host detects the device and the FX3 bootloader issues the chirp signal switch to high speed mode and the speed negotiation is being completed correctly. The host now tries to obtain the USB descriptors and fails (it only worked intermittently on one of our prototypes).
We tried to eliminate cable and connector issues by soldering the USB2.0 D+ and D- leads of the cable directly to the board closer to the chip with no change of behavior.
We followed the hardware design guidelines regarding supply decoupling and signal routing and checked all the supply rails for being stable.
Has anyone seen similar behavior and can at least point us in some direction how to solve the issue, as we have no JTAG connection routed out due to space constraints and are not yet sure where to go from here.