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Hi:
I just use CyControl.exe to test my enviroment.
I have a Xilinx K-7 FPGA and connect with a daughtor board mounted FX3 chip. (connect by Xilinx FMC interface)
I have GPIFII design in FPGA, and want to use CyControl.exe to test Write/Read.
I programed "SlaveFifoSync.img"
And Write seems work, but Read is not good, is there any advice can help me to figure this ERROR MESSAGE?
I attached print screen of the result.
Thanks for help.
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Hi,Hippo
Maybe there is something wrong with your address configuration of your FPGA.Your FPGA can't read data from FX3.Check the FPGA code.
Regards,
Kimia
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Hi,Kimia
Thanks for the reply.
So you mean FPGA can't read data from FPGA.
But BULK OUT works, so FPGA can write data to FX3.
My design only have 2bits FIFO_ADDR.
ADDR only affect Read but Write?
But FPGA implementation slack is 0, so timing seems fine.
And I also check FPGA function with simulation, seems work, too.
Is there any other advice?
Thanks anyway.
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Hi,Hippo,
I met the same problem with you. Finally I found there is something wrong with my FPGA code. What are the numbers of your consummer socket and your producer socket? Actually the fpga shoud read data from the consummer socket and write data to the producer socket.
Thanks,
Kimia
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Hi Hippo,
The error code 997 means that the IO operation has failed.
In this case, the FX3's DMA might not have received enough data from the FPGA.
Can you please probe the flag pins between FX3 and FPGA to check if they get asserted and deasserted appropriately as per your test?
If not please find which flag is not working properly.
This would help you to narrow down the approach of the problem.
Alternatively, you can use debug prints to check if your GPIF to USB DMA channel has received a producer event. (received buffer or not.)
Regards,
-Madhu
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Hi I've got the same problem on Hippo.lee
I've check the signals of control, the are all ok.
But I've still got problem as
BULK IN transfer
BULK IN transfer failed with Error Code:997
BULK IN transfer
BULK IN transfer failed with Error Code:997
As your said, what if the reason of problem is the FX3's DMA might not have received enough data from the DATA,
What kind things should I have to check to solve the problem?
In my case, once the FLAGA and FLAGB are go to hi, then they does not go to the low level. Can you give me any advice or hints? please
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Does that mean BULK transfer in is FX reading data from FPGA and BULK transfer out is FPGA reading data from FX?
If in any case that is possible, how can we send data from a PC to the FX so the FPGA can read the data?
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UP for this !!
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I am using AN61345 as my reference and I am getting confused in using the slave.hex file and verilog code. Correct me if I'm wrong but is the slave.hex for sending data from the PC to the FPGA via FX2LP and the verilog code is for the FPGA to read the data that is sent by the FX2LP?
Also, I get a "BULK OUT transfer failed with Error Code:997" whenever I try to transfer file out. Is there any limit in transfering a data? Can we transfer a picture data using the slave.hex?
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Hi,
In the An61345 project whatever the data that is sent by PC to Ep2(OUT) will be read by FPGA and immediately sent back to EP6 (IN endpoint).You have to read the data from the EP6 from PC .otherwise the buffer will get full and you cannot send data.
I assume that you are using looback verilog code.
Use streamIN verilog code and then you can try sending files.
Regards,
Vikas
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So if we use the streamIN verilog code. What .hex file must we use to program the FX2LP?
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you can use the same hex file.
please read the app note carefully.
It explained clearly about how it works
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I have he same problem as hippo.lee
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HI, I've got the same problem, Did you solve this problem?