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Power Management

SyPU_4767001
New Contributor II

My application is almost the design given on page 28 of datasheet, modified as follows:

CIN0 open, INT = AGND, STBY_LDO = VINT, ENA_LDO = VINT.

R1=0, R2=6.8M, R3=10M => VoutH=5.2V VoutL=3.05V

R4=10M, R5=6.2M => VoutLDO=3V

VBAT= 3V, VoutLDO load = 120uA

When VSTORE2 is low enough to switch from VDD to VBAT mode, I can observe an overshoot of 450mV on VoutLDO when Vout2 is switched from VABT to VSTORE1. What is very strange is that the voltage raises for roughly 50us, then decrease to nominal voltage in 8ms. This is much longer than any time constant given by the R and C of the schematic.

When I raise VBAT, I can observe a second overshoot when Vout2 is switched from lower value of VSTORE1 (V=VoutL) to VBAT. The first overshhoot disappears when VBAT is 5.5V. The overshoot value seems dependant on the dV of VIN_LDO

11 Replies
EijiF_46
Employee

Which device do you use for your application? S6AE102A or 103A.

Please confirm your schematic from Figure 5-1 of board user guide.

https://www.cypress.com/file/234866/download

Especially, The value of VOUT_LDO capacitance and filter capacitor between VOUT_LDO and FB_LDO are important to reduce the overshoot.

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SyPU_4767001
New Contributor II

I confirm I use S6AE102A.

The schematic is the same as Figure 5-1 of board user guide, except R25 = 6.2M, and settings of VOUTH and so on as written above.

I also made another design with R24=1M, R25=620K, C29=2.2nF,  to be able to look at FB_LDO with a scope. I could see exactly the same overshoot on FB_LDO and I guessed it was not related to RC filtering.

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SyPU_4767001
New Contributor II

Hi,

Thank you for reading my request.

I answered on cypress developer community web site.

Sylvain

De : EijiF_46 <community-manager@cypress.com>

Envoyé : lundi 7 septembre 2020 06:47

À : PUGET Sylvain <s.puget@staubli.com>

Objet : Re: - S6AE102A Overshoot on VOUT_LDO

<https://urldefense.com/v3/__http:/www.cypress.com__;!!PxtyCg5I!GMTyqFR9vHr7Lx0QiruL0-HBEaYABglqRHCDhna20K3d7F09eo_M5-mTjijWEcQ$>

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S6AE102A Overshoot on VOUT_LDO

reply from EijiF_46<https://urldefense.com/v3/__https:/community.cypress.com/people/EijiF_46?et=watches.email.thread__;!!PxtyCg5I!GMTyqFR9vHr7Lx0QiruL0-HBEaYABglqRHCDhna20K3d7F09eo_M5-mTPi4QnLg$> in Power Management - View the full discussion<https://urldefense.com/v3/__https:/community.cypress.com/message/249282?et=watches.email.thread*249282__;Iw!!PxtyCg5I!GMTyqFR9vHr7Lx0QiruL0-HBEaYABglqRHCDhna20K3d7F09eo_M5-mTRnLpMyY$>

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EijiF_46
Employee

Refer to Table 8-4 of datasheet as below. https://www.cypress.com/file/215881/download

The input/output voltage difference is Min: 0.3V, therefore your setting of VoutLDO=3V needs more than 3.3V VIN_LDO voltage.

To clearly confirm the overshoot problem, could you change the following voltage more than 3.3V?

VoutL=3.05V

VBAT= 3V

Thanks.

Char LDO.png

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SyPU_4767001
New Contributor II

The overshoot appears when VSTORE1 reaches VOUTH, VOUT2 is switched from VBAT to VSTORE1 and jumps from 3V to 5V. Changing VOUTL do not change anything, even rising VBAT to 3.5V or setting VLDO to 2.7V, in order to have always more that 0.3V drop in LDO.

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SyPU_4767001
New Contributor II

I thing a scope trace will help.

I changed the settings as suggested, with VBAT=3.2V and VLDO=2.7V, 33K load (80uA).

See attached scope capture (yellow=VIDD, blue=VOUT2/VINLDO, red= VOUTLDO)

When VBAT is on, you can see an overshoot, with LDO going back to normal voltage in roughly 20ms.

When VBAT if off (tek00028.png) VOUT fall down immediately and raises also very fast without any overshoot.

The same with a faster time base show a voltage raise with roughly the same slope (tek00034.png) even when VBAT is off (tek00033.png).

See what happens with VBAT=1.5V (tek00033.png). VOUT voltage raises with same slope during same time, stops then converge to normal voltage with time constant given by R and C network of LDO_FB.

For me, we can see 2 strange behavior.

1. Overshoot on VOUT_LDO, depending on VIN_LDO voltage swing

2. Slow return to normal voltage, only after overshoot (slower than capacitor discharge by load).

I ordered some new chips to see if the one I have is defective

Sylvain

De : EijiF_46 <community-manager@cypress.com>

Envoyé : lundi 7 septembre 2020 09:05

À : PUGET Sylvain <s.puget@staubli.com>

Objet : Re: - S6AE102A Overshoot on VOUT_LDO

<https://urldefense.com/v3/__http:/www.cypress.com__;!!PxtyCg5I!FrV1CkxHqTD2xsfrQb_LW6ZYc9GNwrCGuFc3uzWh3x81T3fWULuX7nKYkFpHnys$>

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S6AE102A Overshoot on VOUT_LDO

reply from EijiF_46<https://urldefense.com/v3/__https:/community.cypress.com/people/EijiF_46?et=watches.email.thread__;!!PxtyCg5I!FrV1CkxHqTD2xsfrQb_LW6ZYc9GNwrCGuFc3uzWh3x81T3fWULuX7nKYAxarITE$> in Power Management - View the full discussion<https://urldefense.com/v3/__https:/community.cypress.com/message/249320?et=watches.email.thread*249320__;Iw!!PxtyCg5I!FrV1CkxHqTD2xsfrQb_LW6ZYc9GNwrCGuFc3uzWh3x81T3fWULuX7nKY5fAhd7Q$>

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EijiF_46
Employee

It looks energy shortage of VDD input.  To confirm whether energy shortage, please input the VDD voltage from power supply equipment.

I guess that you can confirm the same problem when a current limitation of power supply equipment changes to lower current.

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SyPU_4767001
New Contributor II

When overshoot occurs, VDD is connected to VSTORE2, VSTORE1 is connected to VIN_LDO. There is no connection between VDD and VIN_LDO.

Using a power supply with high current limit will prevent the chip to cycle from charging VSTOREx and powering out from battery. No switching => no overshoot.

But the normal use of the chip is with a solar cell, which have a low current limit. Using a high current limit power supply do not prove anything.

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EijiF_46
Employee

Refer to the following block diagram for S6AE102A. As you can see, VSTORE2 connects a large capacitor, it does not connects VDD.

Also I recommend to connect VIN_LDO from VOUT2, and VDD only connects the energy input such as solar cell.

Could you reconfirm these connections?

Capture.PNG

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SyPU_4767001
New Contributor II

Yes I confirm.

Sylvain

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SyPU_4767001
New Contributor II

I got it !

I've bought the eval board S6SAE100A00VA1001 and modified it step by step to see if I can observe the same overshoot. Yes I could !

I simply need to change SW22 to high (STBY_LDO) and decrease R21. Even with a little change - I soldered a 10MOhm onto R21 - 6.8M downto  4.0M, I can observe an overshoot. The lower R21, the higher the overshoot. Same overshoot as on my board with a short.

So, I have new questions.

1. What is the highest value for VOUTH ? Whith R21=0, we can have up to 5.2V which is perfect for storing a lot of energy in a 5.6V supercapa. What is the benefit of the supercapa when VOUTH is set to 3.3V and VLDO set to 3V ?

2. What is the max load of LDO in standby mode ? My application requires a mean current of 0.1mA, and 6mA peak for 2ms. As VDELLD2 may be as high as 0.3V for 1uA load, I guess standby mode should be avoided.

Is S6AE102A suitable for my application ?

Load 33kOhm

Supercap 0.1F, value do not matter, assuming voltage is low

VBAT 3V

Solar cell simulated with a 5V supply in serie with 47kOhm

You can observe the overshoot when VOUT2 is switched from VBAT to VSTORE1

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