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PSoC General

fmfm_590656
New Contributor

Hello,

I am using PSOC6 PROTOTYPEKIT BOARD 。
I am using a Verilog file for DS18B20 testing (I got it from a test in Altera Cyclone IV and it works well). But the file cannot be built in PSOC Creator 4.3
The Screenshot in PSOC Creator 4.3.

屏幕截图(318).png

The errors occurred in building
It seems that the PSOC Creator 4.3 cannot interpret the line 171

Can't handle expression 'Z' in the final equation for 'org_data(0)'.

And I do not know how to solve it.

And I wonder whether the Verilog syntax in PSOC Creator 4.3 is just a subet of the Verilog syntax in general.

Thanks in advance.

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MotooTanaka
Esteemed Contributor

Hi,

IMHO, the "Verilog" provided in PSoC Creator is not as full blown as the one in Quartus Prime.

For the language reference, we can refer to

Menu: Help > Documentation > Warp Verilog Reference Guide

 

For a quick fix of the problem, I think that you need to place an output pin with enable

001-GPIO-Config.JPG

and add net/wire for both value of dq_out and enable of dq_out

002-dq_out_pin.JPG

Then when you need to do

dq_out <= 'Z' ;

do

dq_out_enable <= 1'b0 ; // disabling the output, which make dq_out to be 'Z'

dq_out_value <= 1'b0 ; // whatever reasonable value for place holder here

I hope that this will fix the problem you are seeing in the line 171.

But since UDB resource of PSoC 4 is very limited, I wonder if the whole Verilog component can be fit.

If you need to use more UDB blocks, may be you need to consider using PSoC 5LP or PSoC 6.

 

moto

 

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odissey1
Honored Contributor II

fmfm,

There are several examples here on how to use DS18B20 with PSoC. You may check this component

https://community.cypress.com/t5/Code-Examples/Component-to-read-DS18B20-digital-temperature-sensors...

 

1-wire communication with DS18B20  is inherently slow, so using Verilog is not justified. As Motion mentioned above, it will not fit PSoC4 PLD space.

/odissey1

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odissey1
Honored Contributor II

Try existing codes, for example

https://community.cypress.com/t5/Code-Examples/Component-to-read-DS18B20-digital-temperature-sensors...

 

The PLD space on PSoC 4 is not sufficient for Verilog implementation

fmfm_590656
New Contributor


Hello,
Thank you for your advice. And I downloaded the package DS18B20_archive_04.01.2015.zip you uploaded in
https://community.cypress.com/t5/Code-Examples/Component-to-read-DS18B20-digital-temperature-sensors...

Now I try the method you suggested in PSOC Creator 4.3. and it can be complied for PSOC4. But I am using CY8CPROTO-063- BLE PSOC6 MCU KIT BOARD .
And some problems ocurred .
1. some componets in PSOC4 are not compatible with PSOC 6. And I manually changed them.

2. Build error: cytypes.h: No such file or directory. After that, I copyed the cytypes.h manually to the relative path '...\Generated_Source\PSoC6\',
and this error disappeared. I wonder whether it is a proper way to do so.

3. then
Build error: 'CyGlobalIntEnable' undeclared (first use in this function).
After searching the definition file, I see the Macro was defined in CyLib.h,
but it is in the relative path '...\DS18x8_demo1.cydsn\Generated_Source\PSoC4\...‘,and there are two files, CyLib.h and CyLib.c.
And no such files in relative path '...\Generated_Source\PSoC6\'.
Do I need to copy the two files manually to the relative path '...\Generated_Source\PSoC6\'?
But the versions are different. And I do not know how to solve it.

Thanks in advance.

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odissey1
Honored Contributor II

fmfm,

Sorry, the above component is only for PSoC5 and PSoC4. It is unlikely to work on PSoC6 due to use of hardware blocks.

I recommend to check several software-only implementations, available on this forums

https://www.hackster.io/vsrs/psoc4-bit-banging-1-wire-protocol-ds18b20-thermometer-ec7530

 

https://community.cypress.com/t5/PSoC-5-3-1-MCU/ds18b20-code-for-psoc5lp-gives-7degree-drift-in-read...

 

/odissey1

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RodolfoGL
Employee

The PSoC 6 you are using actually has the UDBs (hardware blocks), so the component should be portable to that device.

If you are using a PSoC 6 device without UDBs, I feel it is possible to use a SPI + Smart I/O to implement this. I don't have a solution for that though.

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odissey1
Honored Contributor II

RodolfpGL,

The component uses only a tri-state buffer and Control/Status register for parallel reading of up to 8 sensors. It was specifically made for simultaneous sampling an array of sensors in environmental chamber. For a single sensor, a simple software approach is ok. I am hesitant to port it to P6 due to the future status of Creator IDE. It is unlikely that I will study ModusToolbox for a fun.

/odissey1

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