Detecting ShiftReg input FIFO empty state.

[BuHa_1507271]

I'm trying to use the ShiftReg 2.30 component in the schematic editor.   I'm looking for a output "pin" to tell me if the input FIFO is empty, so I can stall the clock, at least that's how I'm thinking about it.   

The datasheet has a statement saying The Load operation has the hardware restriction that the load event can be provided only when input FIFO is not empty.   It seems unclear to me what happens if the Load input is asserted when the FIFO is empty.   

Since the only output other then ShiftOut is the Interrupt signal, I'm guessing that might be it, but I'm looking to use it in additional UDB logic, rather than feeding it to the interrupt controller.    Can anyone provide more guidance, or a working example link.   

Note: An earlier form posting related to using DMA with ShiftReg seems like it might be relevant, but the link to it seems broken.

[Len_CONSULTRON]

BuHa,

I believe you might have spotted a "typo".   I think the statement you pointed out should be:

"The Load operation has the hardware restriction that the load event can be provided only when input FIFO is not FULL. "

If you look at the ShiftReg_WriteData() API call you'll notice the following highlighted

cystatus ShiftReg_WriteData(uint8/16/32 shiftData)
Description:
Writes data to the shift register input FIFO. A data word is transferred to the shift register on a rising edge of the load input
Parameters:
uint8/16/32 shiftData: Data to be written. Data type is determined by the Shift Register Length parameter.
Return Value:
cystatus: Returns an error if the FIFO is full or CYRET_SUCCESS on successful operation. If the input FIFO is full then the data will not be written to the FIFO.

[RodolfoGL · Accepted solution]

The documentation is correct.

Note that there are two FIFOs in the ShiftReg:

Output FIFO: Read by the CPU. Use the ShiftReg_ReadData

Input FIFO: Written by the CPU. Use the ShiftReg_WriteData

When dealing with the Output FIFO, you just want to read it when the FIFO is NOT empty.

When dealing with the Input FIFO, you just want to write it when the FIFO is NOT FULL. 

The Load signal loads data from the Input FIFO to the shift register. You only want to do that when there is data in the FIFO, so the hardware should only process the Load signal "when the input FIFO is NOT empty".

You can easily modify the UDB component to extract the information you need from the FIFOs. The datapath has all the signals you might want. You can actually refer to the signals that goes to the StsReg.

assign status[SR_F0_EMPTY] = f0_blk_stat_final;
assign status[SR_F0_NOT_FULL] = f0_bus_stat_final;
assign status[SR_F1_FULL] = f1_blk_stat_final;
assign status[SR_F1_NOT_EMPTY] = f1_bus_stat_final;

You can create a new terminal in the component and assign them from one of the signals above.

F0 -> input buffer

F1 -> output buffer