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PSoC Creator & Designer Software

Anonymous
Not applicable

Helloeveryone

         I created verilog component (squarewave generator) and i dragged it and kept in the Topdesign from default tab .If i want to see the output i should give inputs to the component , my inputs are clock, enable.if enable =0 counter start counting otherwise counter stop counting. how to give 1 and 0 to enable pin in topdesign. anyone please help me.

my topedesign

topdesign.PNG

`include "cypress.v"

//`#end` -- edit above this line, do not edit this line

// Generated on 01/31/2018 at 21:29

// Component: clkgeneration

module square_wave(clk,enable,clkout);

   input clk; // assuming 4 KHz

   input enable;

   output reg clkout;

   reg [11:0]  counter; // 12-bit for numbers up to 3999

   always @(posedge clk)

     begin

        if (enable == 1'b1  ||  counter == 12'd3999) // period, count from 0 to n-1

          counter <= 0;

        else

          counter <= counter + 1'b1;

        // synchronous output without glitches

        if (enable == 1'b0  &&  counter < 12'd2000) // duty cycle, m cycles high

          clkout = 1'b1;

        else

          clkout= 1'b0;

      end

endmodule // square_wave

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1 Solution
Esteemed Contributor II

You might use one bit of a control register component.

Bob

View solution in original post

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4 Replies
Esteemed Contributor II

You might use one bit of a control register component.

Bob

View solution in original post

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Anonymous
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THANK YOU

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Anonymous
Not applicable

I need to generate I HZ clock without giving clock as input.in which first 500ms the clock should be high and remaining 500 ms the clock is low this  process is repeated n times.so i need to generate 500ms synthesizable delay. when i searching internet  i saw delay  syntax  #num , but it is only for simulation .how to generate synthesizable delay in psoc by using verilog.

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Esteemed Contributor II

Easiest is to use a PWM component, feed it with 1kHz, use a period of 1000 and a compare value of 500.

Bob

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