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PSoC Creator & Designer Software

JoBr_1593366
Contributor II

It seems like every time I make a change to a schematic, the .cysch.cyvis file gets a raft of meaningless tweaks to component locations at the same time for no reason:

JoBr_1593366_0-1624210015061.png

These clutter up the git history and make it hard to find the actual meaningful changes.  Can this behavior be fixed?

(I don't understand why these are even saved as floats when the wires and components are always snapped to a grid.)

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8 Replies
Len_CONSULTRON
Honored Contributor II

JoBr,

It makes sense that the TopDesign.cysch gets updated when a schematic change occurs.  There is no way to avoid even minute changes like you mention.

The .cyvis file you mention:  I don't see it in any of my designs.  Where do you find it in yours?

If it is not necessary in a design, you can ignore/exclude it from the git archive.

Len
"Engineering is an Art. The Art of Compromise."
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JoBr_1593366
Contributor II

These files are generated when you turn on "Generate Description Files" for the project. They allow you to see what has changed in the git history (since diffs of binary cysch files are useless for this).

There's no reason why the locations and widths of every component should change by small fractions just because, for instance, I renamed one of them, or disabled one of them, without changing the position of anything, but that's what it does. Seems like a flaw in the way the schematic is stored?

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Len_CONSULTRON
Honored Contributor II

JoBr,

I guess I never needed to "Generate Description Files".

Small changes in the locations and widths on a minor schematic change:  Is it a bug or a feature(?)  Don't know.

Len
"Engineering is an Art. The Art of Compromise."
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odissey1
Honored Contributor II

where that "Generate Description Files"  option is located? I can't find it.

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JoBr_1593366
Contributor II

Right-click the project name in Workspace Explorer, go to Properties..., then Generate Description Files to True

It generates plain text versions of the schematic's visual (.cysch.cyvis) and functional (.cysch.cysem) layout.  I use them to see changes in git or to do diffs between different schematics, etc. but it doesn't work great because of problems like this.  It also randomly reorders things, which adds noise to diffs for no change. 

I'm not sure if it's possible to convert the plain text files back into a binary schematic file.

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odissey1
Honored Contributor II

Thank you for info. In which folder should I look for the output file? - Can't find it.

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JoBr_1593366
Contributor II

You have to modify the schematic and save it to generate the first one.  You can then undo the modification and save it again.  (Another quirk of these files that I don't like.)  Then they will be in the same folder as the .cysch.

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DheerajK_81
Moderator
Moderator

Hello @JoBr_1593366 ,

Thank you for pointing this out. Even though the schematic is the same, the way the floats are being calculated is causing this and since it has upto 4 decimals of accuracy (a good thing and a bad thing), the number calculaṭed seems to be minorly different each time. I have passed this on to the software team for evaluation. 

Regards,
Dheeraj