PSoC™ Creator & Designer Forum Discussions

What I'm trying to do is to transfer 80 bytes from a buffer to a FIFO. It kind of works, but not right. I'm using bursts of 4 bytes and a setting to have a DREQ on every burst. So I set the size of 80 and burst size of 4.

CyDmaChSetConfiguration(dmaCh,4, 1, 0,0,0); // avf 4 per burst, req every time

CyDmaTdSetConfiguration(dmaTd, X_BYTES , dmaTd, DMA__TD_TERMOUT_EN | TD_INC_SRC_ADR);

So it loops to the same Td.

My custom UDB gets triggered by a hardware signal every 30 usec and starts sending requests when the FIFO is empty. The DMA sends the data and I get an interrupt on NRQ after (what looks on the scope as) 20 bursts, that is 80 bytes as it should.  I change the pointer to the start of the new buffer to wait for the next trigger event. But I can see that the number of bytes sent is not always 80, so the data is being sent from wrong addresses.  It's possible that my UDB has a bug. If so I'll find it, Verilog is not a problem. The question is it possible that the misalignment happens elsewhere  and more importantly how can I make sure a new set of data will start from the right place?  In another thread I have seen an advice to disable, release and enable again the DMA channel. But will that not hit performance? Is there a way to just reset the address? Also am I right to chain the td to itself or should it be terminated and a new one started after one full set of 80 bytes?

Thanks.

I'm trying to migrate a project from PSoC Creator 3.3 to 4.3, but it doesn't work when compiled in 4.3.  I'm using the same project and source files, just opening the workspace in 4.3, but it doesn't compile to the same .hex file.  Which output files from the build should I compare between the two outputs to find where the discrepancy is?

I uninstalled the PSoC Designer from control panel. Then i released that the uninstall process isn`t complete. I have removed all the files as per suggestions that i found on the community, yet no much luck.

This has prevented me from installing the latest version of PSoC Designer.  Is there a way for me to completely remove the software?

Everytime I launch PSOC Designer I get "Adobe SVG Viewer" error and it indicates I need to install/reinstall.  When I look for SVG viewer I find a 15 year old app for WIN98/XP.  I would very much like to resolve this error so I can access pinout view and other.

I'm having trouble using the port interfaces in the PP_COM_Wrapper dll that PSOC Programmer provides. I am using a CY8CKIT-0529 PSOC 5LP prototyping kit. I am able to successfully open the port to the board and have verified that I can write to it using the USB-I2C bridge. However, when I go to close the port or check if the port is open the commands returns that the port is closed. For the closeport() command it returns -1 and "Port is not opened!" For the IsPortOpen() command, it returns a 0, which means the port is closed, and no error message. I can still write to the board via I2C after running both commands. Any feedback on why I am unable to close the port and why the program thinks the port is closed would be appreciated. Am I missing a use of the command?

Working with Creator 4.3 has been going well until Windows 10 was upgraded over-night.  Now the message "Can't Open CMSIS-DAP port" comes up whenever trying to compile.  I've run the PSoC 4.3 repair  and also the PSoC Programmer repair.  But, no luck so far.

Any ideas as to how to get over this?

Hi all,

I have a circuit that uses a battery type NCR18650PF with the relative charger mounted on breakout 03962A which uses the 4056E regulator.

I have to supply a CYBLE-012011-00 type module. I was thinking of two solutions.

The first: put the 03962A output, between out + and out-, a low consumption linear regulator, let's say 1.8V output. In this case I would have a current consumption as well as additional components to add.

Second solution: supply the CYBLE module directly between out + and out-, since the charging voltages are within the tolerance limits of the module. So I would have the advantage of not having added current consumption and components.

Can anyone give me some opinion?

Thank you!

Hello.

I am introducing myself into the automotive field and I am working with PSoC4 + CY8CKIT-026. I am working with the LIN protocol and I have done some developments. I would like to know if is there any tool to use in PSoC Creator which allows me to test the MISRA-C Compliance.

Hi, I can't seem to find the file referenced in Designing PSoC Creator Components with UDB Datapaths, Project #3 - Simple UART. Page 39 of the pdf. Can someone please point me in the right direction?

Thanks,

Mike

Hi,

I'm following the example in "PSoC 4100S and PSoC 4100S Plus - PSoC 4 Architecture Technical Reference Manual (TRM)" (par.27.7), to write flash avoiding the blocking; infact the erase/write operation in flash required about 12-20ms, and during this time the CPU is stopped there.

The example shows the mode to avoid this blocking, in particular it is necessary to run code in sram (at least the routines used for the scope) also the interrupt service routine for SPC has to be in sram.

In my project (here attached), I was able to move the routine in sram, I define also the SPC interrupt and redirect its vector address, but this interrupt never happens,  I try to read the register CPUSS SYSARG to check the error code, but with Miniprog3 debugger this register seems to be not readable (I see #######... instead of value), but I can access to CPUSS SYSREQ , there I read the last command sent (0x00000007) really with bit31 =0, the command had bit31=1, seems that it becomes 0 due to interrupt management, the question is who, where?.

In the original example is required to have Clock to 48MHz, but the device I'm using CY8C4125AXI-S433 has 24MHz as max value, could be it the problem?

Someone has had similar problems?

Thanks in advance

Renato