For a hierarchical Verilog design I'm trying to `include a file from the same directory as the current file. It works with an absolute path `include "C:\Blah\foo\bar\baz.v", but I can't `include "baz.v" to work.
Can this be done? Any setting or workaround? Unfortunately I didn't find a solution in the forum, just similar questions.
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Hi,
I have a program with PSOC5 where I have a multichannel ADC. I want to be able to configure the zero error and gain of each channel individually so that I can use the below code.
for(i=0; i<No_of_ADC_Channels;i++)
{ Actual_ADC_Reading [i] = (Instant_ADC_Reading[i] + Zero_Error[i])*Gain_x100[i]/100; }
------------------------------
And have a definition such that
Zero_Error[0]=100;
Zero_Error[1]=30;
Zero_Error[2]=-70;
.... and so on.
I have been simply using variable arrays to store Zero_Error and Gain_x100 but I am sure that there is a better way to do this.
Obviously I can't use #define.
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On my PC I had to replace the D drive where Creator was installed due to a hardware fault of the drive.
Then I could install PSoC Creator 4.4 successfully, but two problems remain.
1) Update manager: When I start the update manager, the message
"PSoC Creator errro fmk.M0027 Unable to start executable image: (C:\Program Files (x86)\Cypress\Cypress Update Manager\cyliveupdate.exe)", see attached image.
pops up. I installed Creator on the D drive. There is no directorxy named "Cypress Update Manager" nor a file named "cyliveupdate.exe" on the disks.
When I click "Show Details", it says that there is an internal error.
2) Select Debug Target.
After selection of Debug - Select Debug Target, a window "Select Debug Target" pops up as usual. But there is nothing in this window. See attached image.
I am an experienced user of Creator, and I have PSoC Creator 4.4 installed on other PCs successfully, everything is fine there.
As said above, on this PC, I had to replace the D drive due to a hardware fault on the drive. Maybe Windows got confused because Creator (and other software) suddenly disappeared. I uninstalled everything that was possible, deleted all Cypress files from the disks, cleaned everything from Cypress from the registry, installed and uninstalled Creator several times, still the same problem.
All ideas are welcome since I do not like the idea to re-install Windows completely...
Show LessI see that there is a binary blob in openocd/contrib/loaders/flash/psoc4/psoc4_current_write.inc.
This data is referred to as containing the programming algorithm when it is included in the p4_current_algo[] array inside psoc_write_inner(). It is then copied into a working area in the target memory.
But I do not understand what exactly is in this binary blob. How is it derived?
I don't see any place in the psoc4.c code where a SROM request happens for PSOC4_CMD_WRITE_ROW (0x4). Thus I have been trying to understand how the data actually gets written to user flash.
I would appreciate any insights you can provide.
Hi,
I Have a critical error which have popped up and I cant get rid of it. I have a project for a PSOC 4200 BLE MCU, where a use the upgradableStack project. I have added a new application project to this and I am getting this error:
Error: prj.M0266:
Shared code exported by instance CyBle of component BLE_v3_66 is not identical to code expected by instance CyBle of component BLE_v3_66.
(App=psoc_creator)
This currently prevents us from exporting the project to eclipse, for further development at a critical stage in the project.
Any help is much appreciated !
regards,
Martin
Show LessHello,
I'm not too familier with PSOC terminology yet, so I hope you can understand me:
I'm using a PSOC 5 LP prototyping kit - the stick kind.
How can I get the ADC values out of the ADC so I can use them in hardware?
I think it might be better to draw a picture:
To be clear: I've gone through the ADC to UART example. From my understanding of how PSOC works, this is not what I want. From my understanding, the main loop runs at about 1 KhZ, and I want to be able to access the full 1 MhZ ADC sampling rate. From my understanding, if I want the full 1 MhZ, then I need to create everything in the top design file, not programatically.
Am I under the correct understanding that whenever I enter something into Main(), it gets executed on the microcontroller portion of the chip?
Best Wishes,
-TJP
Show LessI have a power button which cause interrupt and wakesup the system from Deep Sleep.
I would like to add, even only when the system is on (not a sleep), sort kind of filter, Debouncer or even just the D-FF the filter noise.
the problem is that those components require a clock and when I tried to add it even with Control Register which is initialized to transfer the signal from the
Show LessThe install seems to want to write files outside of the install directory, so windows 10 security is blocking that, as it should. I selected the E: drive for the install. No surprise the install can't find files on the C: drive. My C: drive is full.
Show LessHello
I am usin PSoC Creator 4.3 with BLE 4200 device.
Why cant't change the setting 'Parity' in UART Basic tab (if select IrDa mode)?
Is this how it should be?
Thanks.
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Hi every body. I want to run an TCP/IP ethernet with ENC28J60 and CYC4245AXI-483
is there any body that have an example to share with me?
any samples that I founded is about psoc3, when I changed chip selection from psoc3 to psoc4 several errors occur. It is cause to confuse me to run and understand.
As a basic view point I need to understand how does ENC28J60 with their registers to have an TCP/IP ethernet network building. In addition what can I do to manage control and buffer registers of ENC28J60 as well as to work well.
please guide me...
thanks for attention...
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