PSoC Creator & Designer Software

hi,

i found  a problem  using the rx hw fifo buffer,

if i read a byte from the fifo and in that exact time anew byte is recived the data i read i corrupted.

is there any way to read the fifo without that problem?

thanks.

Hi, the blog info, which was quite useful, seems to have been removed.

Would it be possible to create a HTML file of all the content for users to access or download ?

https://www.cypress.com/blog/psoc-sensei-blog

Regards, Dana.

I am building for PSoC 6, and PSoC Creator 4.4 insists on generating IAR and MDK files which I have no use for - and just clutter up an already very cluttered Workspace explorer.
The only message I could find about this is:  https://community.cypress.com/t5/PSoC-Creator-Designer-Software/code-setup/td-p/129401?start=0&tstart=0
Which does NOT resolve or fix the problem. If the only possible solution is to recreate a very complex workspace from scratch, I won't bother.
My project is (at present) 002-16767_CE216767 PSoC 6 MCU Bluetooth Low Energy (BLE) Device Firmware Update (DFU).zip, so please DO NOT ask me to upload my project - you already have access to it.
Here is my build settings, so you don't have to ask for it:

And here is an obvious example of the problem: PSoC Creator generates 3 new files (for 3 IDEs) for each of two projects within the workspace:

OK, now just to reiterate, so I don't get the standard non-answers: You already have access to my complete project, BECAUSE IT IS ONE OF YOUR EXAMPLES, and I have provided a screen shot of my Build Settings, SO PLEASE DO NOT ASK FOR IT.

Hi, anyone have a copy of the ISO disk or just the SP1 for PSOC Creator 1.0. ?

Also any other SP's for that version of Creator would be welcome.

It not in the archive area for PSOC Creator.

Regards, Dana.

Hi all,

I recently started working with a PSoC 6 development kit (CY8CPROTO-063-BLE). As I was familiar with PSoC Creator for PSoC 5LP, I started developing simple projects targeted to PSoC 6 devices using PSoC Creator 4.4.

The problem is that the build and programming steps are painfully slow on my machine, while being very fast when using PSoC 5LP as target device. Do any of you know what could be the cause of this behaviour?

Here are the specs for my machine:

- MacBook Pro: dual-core 3.1 GHz Intel Core i7, 8 GB RAM

- Windows 10 VM running on Parallels with dual-core, 3 GB RAM

Thanks,

Davide

I am attempting to incorporate the Renesas ZMOD4410 IAQ functionality into a PSOC 4200M project. Calls to some of the floating point functions in newlib libm and libgcc consistently cause a hard fault. I have been working with Renesas support to resolve the issue and they suggested a possibility that there is a mismatch between either the version of the GNU compiler or command line flags between the IAQ libraries and the PSOC libraries.

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Last details sent to Renesas:

I did some testing and have attached some screenshots of the details of the failure with the configuration included in the optimization, linker, and Stack/Heap configuration shown in the screenshots. The bl_dmul screenshot shows the instruction that causes the hard fault and the stack_trace screenshot shows the stack at the beginning of the error handler (handler.jpg). This set of traces are for no optimization and the fault consistently occurs on the d_mul instruction.

I found that changes to the optimization level changes the actual instruction (which is still consistent for each optimization level) that causes the fault. No matter what the optimization levels, the instruction that cause the error is always in the libgcc or libm floating point routines resulting from a call from calc_iaq_2nd_gen_internal().

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I have attached screenshots with additional details.

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Last details from Renesas

Here is the details that Renesas provided on the compilation of the IAQ library.

• Compiler version: We use 7-2018q2 version. Can you check for an update of your compiler?
• Our additional/differing flags are: -static -O3 -std=gnu11 -fsigned-char -fdata-sections; We do not use -ffat-lto-objects. On the description of the options I don't see any issues with the different options

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Any suggestions on how to proceed?

thanks,

pete

I have a project with a Cy8C4013SXI-420. This is a SO8 part.

I have the programming configuration as:

1.6MHz (also tried slower)
3.3V
Power Cycle Mode
5 Pin Header
SWD

I have the following wires connected from the MiniProg3 to my target board:
VTARG to my 3.3V rail (PSoC supply). No other power applied to the board. There is no other significant load on this rail, maybe 30mA.
GND to GND of course
SCLK to PSoC pin 1 (P3_1)
SDAT to PSoC pin 8 (P3_0)

The programmer cannot connect. It takes a long time, like 30 seconds, then shows the target as "Cortex-M0", but won't connect. Sometimes it doesn't even show that.

Put a scope on VTARG and it is slowly cycling on and off to 3.3V.

I have changed the chip, same result.

I have had similar issues with the standard 5 pin programming interface before, but only when I have needed to put wires to extend the programming interface. I have found that it will NOT detect the target if those wires are more than maybe 2" long. So in this case, because I have wires, they are about 1 inch long.

Anyone have a solution for this?

Thanks in advance -

I have 1 CY8CKIT-050  and 2 CY8CKIT-030 boards, all no longer CPU supported

by Creator. Do you folks have a service that can update CPU on the board to

latest rev for a fee ?

Tossing these boards would be a sin and an act against engineering humanity 🙂

Regards, Dana.