PSoC Creator & Designer Software

Customer application where he is relying on ARM when power off GPIO will be in HiZ state.

Two cases to this to consider, Power disconnected (switch opens to PSOC Vdd) or power collapses,

such as in a transformer fed simple bridge > regulator PSOC, where PSOC power pin is always "in circuit,

connected".

Ap notes do not discuss this. I stated to customer than when Vdd drops below its min datasheet spec  value

all bets are off as to what a GPIO pin looks like. That there is possible charge trapping inside device driving gate 

that would have to bleed off to make sure a device, in this case the NMOS side of totem pole, and that could take a 

long time.

Question, what is the state of a GPIO pin, and can it be controlled, pre destined, when Vdd drops below operating

datasheet spec value ? I think answer is NO !

Regards, Dana.

I have 1 CY8CKIT-050  and 2 CY8CKIT-030 boards, all no longer CPU supported

by Creator. Do you folks have a service that can update CPU on the board to

latest rev for a fee ?

Tossing these boards would be a sin and an act against engineering humanity 🙂

Regards, Dana.

I'm using the WFlash of a PSoC 6 for emulated EEPROM in a current project.  I've noticed a problem in that every time I program the processor, it overwrites the WFlash sector.  I seem to be able to avoid writing this section when I load the code through the PSoC Programmer software, but cannot find the means to do the same when programming through PSoC Creator 4.4.  Is this option hidden somewhere that I haven't seen or is it just not possible?  I'd rather not have to switch over to PSoC Programmer every time I want to flash a new build in order to maintain EEPROM values.

In a design with combinatorial logic on an PSoc 4 device I run into a placement problem which boils down to the following issue:

An combinatorial enable signal, which is used in several places, like here, p7:

is inserted into another term during synthesis and optimization:

Note: Expanding virtual equation for '\FOO_1:enable\' (cost = 2):
\FOO_1:enable\ <= ((not Net_48 and Net_49 and Net_47));

Note: Expanding virtual equation for '\FOO_1:p7\' (cost = 60):
\FOO_1:p7\ <= ((not Net_48 and not Net_38 and not Net_37 and Net_49 and Net_47 and Net_31));

The the digital placement fails with:

W2555: UDB : UDB_0 (PLD : 1) contains 14 data inputs. Maximum allowed 12.

I know that it would fit if the enable signal would go to another PLD and p7 would use enable instead of (not Net_48 and Net_49 and Net_47).

I tried to play with opt_level and placement_force, but these don't seem to help here even though I see they are recognized in the rpt file. However the expansion during synthesis is still done.

Is there a way to avoid this? Something like optimizer settings or explicitly saying that enable must be kept and not expanded into other terms?

Dear SIr/madam,

                      doubts regards program loading using JTAG Protocol.

using PsoC5LP family mc CY8C5868AXP-035 , program through miniprog4. but in miniprog4 we cant choose JTAG  protocol, default SWD protocol only coming. by using the setup, i want to load .hex file using JTAG protocol. give some suggestions.

Hello

I see what may be a conflict in the Fan Controller datasheet where manual mode seems to suggest only the ability to use the PWM Duty cycle API and there is no response to fan speed, but a graphic further down in the sheet seems to imply that the desired fan speed API can be used in manual mode.

So I really need a clarification, before I start writing code.

Thanks

Since the previous topic titled "ISR build errors"  was closed, I am opening the new thread. DatasheI tried most of the solution on that post but still seeing peculiar behavior of the debugger.

After If (flag == False)Before If (flag == False)Suggested in the previous thread
Following is the code 

From the watch window we could see that the value of flag is false but still it will not go into the if condition.
if(flag == FALSE || flag == false)
{

flag = TRUE;//Message begins

//Valid starting sequences

}
else if(flag && rx_i == rx_len)

flag = FALSE;//message ends


else

rx_i=0;flag=FALSE;//garbage received ignore the message
continue;

}

Kindly let me know how to resolve the ISR issue.

I have a project with a Cy8C4013SXI-420. This is a SO8 part.

I have the programming configuration as:

1.6MHz (also tried slower)
3.3V
Power Cycle Mode
5 Pin Header
SWD

I have the following wires connected from the MiniProg3 to my target board:
VTARG to my 3.3V rail (PSoC supply). No other power applied to the board. There is no other significant load on this rail, maybe 30mA.
GND to GND of course
SCLK to PSoC pin 1 (P3_1)
SDAT to PSoC pin 8 (P3_0)

The programmer cannot connect. It takes a long time, like 30 seconds, then shows the target as "Cortex-M0", but won't connect. Sometimes it doesn't even show that.

Put a scope on VTARG and it is slowly cycling on and off to 3.3V.

I have changed the chip, same result.

I have had similar issues with the standard 5 pin programming interface before, but only when I have needed to put wires to extend the programming interface. I have found that it will NOT detect the target if those wires are more than maybe 2" long. So in this case, because I have wires, they are about 1 inch long.

Anyone have a solution for this?

Thanks in advance -