PSoC™ Creator & Designer Forum Discussions
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I using CY8CKIT-009 Kit with CY8CKIT-001, Psoc CY8C3866AXI-040. I can not schedule with psoc programmer from version 4.0 to 5.1, and when I try to use the psoc creator 2.1, it's wrong. When I use version 3.13.4 psoc programmer, he can program, but when using the vo pcoc creator 2.1 it says the device is being used by another program, and only he is open. I configure the 2.1 psoc creator gave the message: Warning: dbg.M0039: There was an error running port acquire . There may be the devices attached, or the device may be in use by another application "and does not constitute giving psoc programmer busy and soon fail. thanks. |
Hi all
This component is simple 8bit Wolfram cellular automata.
Double click component set rule parameter 0-255 (default 30).
dout output is 8bit CA value
q output is 1bit result (if dout = rule then value q=1)
Kamil
Show LessHi all
This component is simple 8bit Wolfram cellular automata.
Double click component set rule parameter 0-255 (default 30).
dout output is 8bit CA value
q output is 1bit result (if dout = rule then value q=1)
Kamil
Show LessEnjoy, at your own risk of course, but it's free to use. It seems to work 🙂 . Feel free to add your constructive criticisms. Both the SR and JK latches are in the workspace. I really do not know how to make this these standalone library components.
Show LessLooking through the TRM for the PSoc 5 and the Switched Capacitance op amps, I notice that there exist either a 400 femtofarad or an 800 femtofarad cap on the input, and a selectable feedback resistor ( I believe 20k =<Rsub_f=< 900k). Is it possible to get these put together to make a differentiator? We obviously have the option to make an integrator/TIA, but it would be nice to be able to use the differentiator at the very least for edge detection. Can this be done? If not, could we get this option for Creator 2.1x purty please Cypress?
Show LessIn workspace explorer, source view, cannot right click a listed resource name and copy to clipboard.
Same for tab of that resource.
Useful for getting help with routing and compile issues.
Regards, Dana.
Show LessHi again folks. In my novice naivete I've led myself to believe that a looping/cyclic chain DMA will issue a "done" flag once it hits the end of the last burst of the last TD. But, this doesn't ever seem to happen...it seems my DMA loops without ever issuing a "done" flag. Is this the correct behavior, or am I missing something? I'd really like to be able to keep tabs on the status of the DMA this way. Thanks all.
Show LessFirst!
Yeah, I know, an SR latch is pretty lame. Blame Robert, he challenged me to do it (and it was indeed a challenge given my limited mental capacity). Enjoy anyway, but at your own risk, I have no idea what I'm doing. The Verilog synthesizer "cut the loop" and I have no idea what that means...the whole point was for this thing to have feedback and an undefined state when S=R=1. It seems to work properly on my CY8CKIT -050. Someone smarter than me can tell me what it actually synthesized, I have no idea how to check that.
Show LessNot a big issue, but I find myself wanting to look at component catalog
w/o opening a project. I would like to do it with Creator open, no project
open.
Or better yet, a separate program install as a program in Creator directory.
Regards, Dana.
Show Less