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Hi,
I've had some Top-level designs and components yield some Application Build errors.
If possible, it would be desirable to change the NetList error checking algorithm. I receive the error:
ADD: sdb.M0018: error: Multiple drivers on signal "Net_xxxxx", bit(s) "y".
Here is the condition where the error occurs:
There are occasions when I disable a component with one or more outputs. This occurs at the TopDesign level or in the .cysch file of a component. When I wire around the disabled component or place other non-disabled component outputs on the same signal, I get the above error message in the Application Build phase.
I either have to add a Virtual mux or delete the disabled component to prevent the error.
Suggestion: It would be desirable for the NetList error checker to determine that the disabled component has no valid outputs and that the error message should not be thrown because of this component.
"Engineering is an Art. The Art of Compromise."
Solved! Go to Solution.
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PSoC Creator & Designer Software
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Dear Len-san,
Your suggestion sounds nice.
For the time being, I tried the following workaround (or kludge).
(1) Create 3 schematic pages
page_1
page_2
page_3
(2) disable page_3 and generate application
worked OK
(3) disabled page_2 and enabled page_3
received the following dialog,
I selected [OK} without changing the wire name
(4) generate application
worked OK
(5) workaround or kludge in source codes
As we can check <page_name>__DISABLED variable,
we could write program
#if !page_2__DISABLED
/* code for page_2 component(s) */
#endif
#if !page_3__DISABLED
/* code for page_3 component(s) */
#endif
Well, I must admit that your suggestion is much better though 😜
Best Regards,
28-Jan-2021
Motoo Tanaka
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Dear Len-san,
Your suggestion sounds nice.
For the time being, I tried the following workaround (or kludge).
(1) Create 3 schematic pages
page_1
page_2
page_3
(2) disable page_3 and generate application
worked OK
(3) disabled page_2 and enabled page_3
received the following dialog,
I selected [OK} without changing the wire name
(4) generate application
worked OK
(5) workaround or kludge in source codes
As we can check <page_name>__DISABLED variable,
we could write program
#if !page_2__DISABLED
/* code for page_2 component(s) */
#endif
#if !page_3__DISABLED
/* code for page_3 component(s) */
#endif
Well, I must admit that your suggestion is much better though 😜
Best Regards,
28-Jan-2021
Motoo Tanaka
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Moto-san,
Thank you. I've operated with copying schematics pages and disabling ones.
The issue is more critical when I'm trying to create components with conditionally enabled/disabled sub-components.
"Engineering is an Art. The Art of Compromise."
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My wishlist: it would be nice to have project pages conditionally enabled/disabled, particularly new component schematic pages. Should not be that difficult to implement.
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Hi @Len_CONSULTRON, @odissey1,
Thank you for providing your feedback! We greatly appreciate it.
I will be creating an internal ticket so that our development team can evaluate your enhancement request. However, it is unlikely that a new feature will be added to PSoC Creator at the moment.
Rakshith M B
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Rakshith,
Understood.
"Engineering is an Art. The Art of Compromise."