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PSoC Creator & Designer Software

Contributor

I want basically the same thing, except with asynchronous set from input, and then output is ORed with input so the output pulse length is at least 1 clock cycle, up to the input pulse length.  There's probably a simpler circuit with a flip-flop or something but I couldn't think of it.  Similar to a retriggerable monostable multivibrator

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Esteemed Contributor II

You could write a small state-machine using an LUT component.

   

Alternatively build a new component using the UDB-Editor to create a state-machine in verilog. That's a new experience 😉

   

 

   

Bob

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Esteemed Contributor II

You could write a small state-machine using an LUT component.

   

Alternatively build a new component using the UDB-Editor to create a state-machine in verilog. That's a new experience 😉

   

 

   

Bob

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Contributor

This works:

   

 

   

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