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# PSoC Creator & Designer Software

New Contributor II

For a hierarchical Verilog design I'm trying to include a file from the same directory as the current file. It works with an absolute path include "C:\Blah\foo\bar\baz.v", but I can't include "baz.v" to work.

Can this be done? Any setting or workaround? Unfortunately I didn't find a solution in the forum, just similar questions.

1 Solution
Esteemed Contributor

Hi,

When we add a Verilog component, PSoC Creator seems to create a new folder/directory for the component.

As I created "mysubmodle" Verilog item,  "mysubmodule" folder was created in the project folder,

just like the "component01" folder.

So I modified the 'include line as

include "..\mysubmodule\mysubmodule.v"

Next seeing the component01.v and mysubmodule.v

I changed the module name from "one_bit_full_adder" to "mysubmodule".

Then I could "Clean and Build" the project.

moto

4 Replies
Moderator

Hello @Skoe

Can you please provide more details about where are you trying to include the file?

Have you created a custom component and are trying to include the verilog file as a part of the component?

In case you want to include a verilog file in your project:

> Right click on the project in the Workspace explorer.

> Click on Add > Existing item

> Navigate to the file directory and select open

I am not sure if this is what you are looking for. If you could provide more information regarding the issue, I would be able to provide a more precise answer.

Best Regards

Ekta

New Contributor II

Hi Ekta,

thanks for your response. To demonstrate the issue I added a minimal project.

component01.v is a Verilog implementation for a component. It uses a submodule from mysubmodule.v. This works fine, but only if I use an absolute file path (see content of component01.v).

It looks like it is supported by the underlying tools, but the GUI does not provide an include path. It even does not add the other file to the exported bundle, I added it manually to the ZIP file.

Is there a way to support a hierarchical Verilog design? It would be unfavorable to be forced to draw symbols and wires when we need to instantiate submodules.

Esteemed Contributor

Hi,

When we add a Verilog component, PSoC Creator seems to create a new folder/directory for the component.

As I created "mysubmodle" Verilog item,  "mysubmodule" folder was created in the project folder,

just like the "component01" folder.

So I modified the 'include line as

`include "..\mysubmodule\mysubmodule.v"

Next seeing the component01.v and mysubmodule.v

I changed the module name from "one_bit_full_adder" to "mysubmodule".

Then I could "Clean and Build" the project.

moto

New Contributor II