I seem to be having a bit of trouble including Verilog header files.
That is to say the include directive itself works just fine. The trouble is that the build tool doesn't seem to pick up on the resulting dependencies and so does not resynthesize on changes to the included files, nor have I spotted anywhere to enter additional manual dependencies. Adding the headers to the project only seems possible as dummy modules and does help either.
Another niggle is the local directory not being on the default include path. Attempting to pass the additional path to Warp via the custom synthesis options and the "-i" option results in complaints about missing options files which I don't quite understand.
To be honest I may be adopting C patterns out of habit and there are probably more natural ways of partitioning Verilog code to share common definitions and functions.
Incidentally is it possible to invoke only the "Generate Application" build step on the command line? I am using IAR to write the code and the full pre-build step of recompiling the generated C code is a bit time-consuming while tweaking the HDL.
Solved! Go to Solution.