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PSoC Creator & Designer Software

ETRO_SSN583
Esteemed Contributor

Hi, trying to implement a 64 bit shifter in Verilog. Its working but need

aid on one problem. I need to pass a 64 bit parameter value to be used

for presetting the shifter, and when creating the component there is

no choice offered for a 64 bit value. Its partially working with a 32 bit 

type so code is fine, just this size issue.

 

I know I could pass it as two 32 bit parameters, buts thats tacky.

 

Parameter is InitPatt

 

Any suggestions welcome to the old and feeble.....:)

 

//`#start header` -- edit after this line, do not edit this line
// ========================================
//
// Copyright YOUR COMPANY, THE YEAR
// All Rights Reserved
// UNPUBLISHED, LICENSED SOFTWARE.
//
// CONFIDENTIAL AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF your company.
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 06/08/2021 at 10:16
// Component: Shift64
module Shift64 (
	output [63:0] dataout,
	output  serout,
	input   clkin,
	input   clrall,
	input   loadall,
	input   serin,
	input   setall
);
	parameter InitPatt = 0;

//`#start body` -- edit after this line, do not edit this line


//    wire [63:0]paraout64;
    reg  [63:0] sreg;                              // actual register

    assign dataout = sreg;
    assign serout = sreg[0];
    
    // reset and load are both syncronous
    always@(posedge clkin)
    
    begin
    
        if (clrall == 1'b1)                         // clear / reset has precedence
    
            sreg <= 64'h0;
        
        else  
        
        if (setall == 1'b1)
        
            sreg <= 64'hFFFFFFFFFFFFFFFF;           // set shift reg to all 0's
        
        else
        
        if (loadall == 1'b1)                        // Load user preset/config data
        
            sreg <= InitPatt;
            
        else
        

            sreg <= { serin, sreg[63:1] };          // Do a one bit shift and take in SerIn bit
    
    end

//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line

 

Regards, Dana.

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26 Replies
RodolfoGL
Employee

You are going to consume a huge amount of PLDs using "regs" in verilog.

You are better off using datapath to implement a 64-bit shift register. You can cascade two 32-bit shift registers.

You can also easily pre-set the register with any value.

ETRO_SSN583
Esteemed Contributor

Thanks I am aware of that tradeoff. Do you have any idea of the speed compromise

using datapath ?

 

Still begs the question how does one enter a 64 bit parameter in user config....?

 

Regards, Dana.

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RodolfoGL
Employee

There is no compromise using datapath in terms of speed. The datapath can also be clocked by the same clock signal from your logic.

There are a few ways to solve the 64-bit user config. For example:

1) Write to 32-bit to datapath FIFO A

2) Write to 32-bit to datapath FIFO B

3) Use the FIFO B level signal (not empty) to load from FIFO to the shift register. 

Len_CONSULTRON
Honored Contributor II

Rodolpho,

I agree.  The datapath method should be a compile-time solution and should not impede operational speed.

Are there any examples that we can reference that use your recommendations?

Len
"Engineering is an Art. The Art of Compromise."
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ETRO_SSN583
Esteemed Contributor

I must be missing something. The Datapath is a state machine with clock executing

instructions, versus straightforward Verilog clocking a bunch of flops. So why

would speed not be affected ?

 

Correction, I see the error in my thinking. The if else structure in Verilog

insures that when anyone condition is satisfied thats done in a clock cycle.

UDB because of address order for the instructions accomplishes the same, so

machine essentially runs at the rate of the clock. Like the old 2900 bit slice

stuff.

 

OK, I will go back to sleep now.....:)

 

Regards, Dana.

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Len_CONSULTRON
Honored Contributor II

Dana,

I've never had a need to work with the Datapath tool.   It is my understanding (hopefully correct) that the Datapath tool allows you work with an existing Verilog file and allows the designer to assign Verilog elements to specific HW registers.  In you case, you'd want to associate the two 32-bit shift regs and assign them to contiguous registers to allow for a single 64-bit load from code.

Let me know if I'm incorrect. 

Either way, please let people following this thread know how you solved your issue.

I have a potential project that currently uses two 32-bit shift registers and I'd like to load them as one 64-bit shift register preload value. 

Len
"Engineering is an Art. The Art of Compromise."
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ETRO_SSN583
Esteemed Contributor

The datapath is more than just registers -

 

 

ETRO_SSN583_1-1623257154809.png

 

On the 64 bit parameter I have two thoughts -

1) Instantiate a definition into Creator integer definition file, maybe tool

would then show all ints/words as a choice. Question is will the compiler

choke on the work around.

2) Define parameter as a string and apply what in effect is code to

test and convert it

 

Regards, Dana.

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Len_CONSULTRON
Honored Contributor II

Dana,

I bow to you.  You have a lot more experience than me in this.

I was also noting some about using the "Directives" in the DWR.   Don't know if this would apply.

Len
"Engineering is an Art. The Art of Compromise."
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odissey1
Honored Contributor II

Dana,

I would go with RodolfoG suggestion using two sequential 32-bit ShiftRegisters. This is a simplest solution. I believe that there only CY_SET_REG32() instruction, no 64-bit version available. So it will not be atomic anyway.

/odissey1

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ETRO_SSN583
Esteemed Contributor

The SR in Creator is not parallel out....unless I am missing something.

 

Regards, Dana.

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RodolfoGL
Employee

You need to create a customized shift register (or customized the one that comes with PSoC Creator).

The datapath has an option to expose the internal register to a parallel out.

There are some complications though. You can't create a 32-bit datapath with the parallel out. It needs to be 8-bit. So you would need to create 8x 8-bit datapath (64-bits) and manually cascade them. You can also place them together, so you can simply write to the FIFO with one 32-bit write.

Refer to the Component Author Guide. Section 4.3.4.2 talks about datapath. You need to use the cy_psoc3_dp, which exposes the "po()" signal. If you use cy_psoc3_dp32 or even cy_psoc3_dp8, that signal is not exposed.

Some useful posts:

https://community.cypress.com/t5/PSoC-6-MCU/Error-when-trying-to-assign-po-for-a-datapath/m-p/173316

https://community.cypress.com/t5/PSoC-5-3-1-MCU/UDB-parallel-in-out-confusion-about-internal-timing-...

https://community.cypress.com/t5/PSoC-5-3-1-MCU/Difficulties-using-the-parallel-input-bus-PI-in-UDBs...

 

Len_CONSULTRON
Honored Contributor II

/odissey1,

There is no 64-bit instruction.  However if the 64-bit load was done with a DMA to sequential addresses it would be nearly atomic.

Len
"Engineering is an Art. The Art of Compromise."
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RodolfoGL
Employee

Using CPU is faster than DMA. You would be better off simply writing to the shift register FIFO directly than triggering a DMA. It is only two writes any way.

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ETRO_SSN583
Esteemed Contributor

Interestingly enough GNU has 64 bit values in it.

https://www.gnu.org/software/libc/manual/html_node/Integers.html

 I cant seem to find any limitation in Verilog on size.... warp verilog the problem ?

 

Regards, Dana.

 

 

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Len_CONSULTRON
Honored Contributor II

Dana,

Yes 64-bit declarations exist in theory.   However the ARM is a 32-bit processor and all memory accesses are 32-bit at most.

Len
"Engineering is an Art. The Art of Compromise."
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odissey1
Honored Contributor II

Dana,

What output speed are you looking for? What PSoC5 chip do you have which has 64 pins?

 

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ETRO_SSN583
Esteemed Contributor

I used 5868AXI-LP035

 

Regards, Dana.

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odissey1
Honored Contributor II

Dana,

Attached are two projects showing 32- and 64-bit ShiftRegister, realized in Verilog (PLD). To load data they use custom component ControlReg32, which is simple combination of 4 Standard Control Registers. The writing is not atomic, but might suffice. To load 64-bit data, two 32-bit ControlReg32 are used. To test content of the ShiftReg32, another custom component StatusReg32 is used. It is also consists of 4 standard Status Registers, so no magic here.

As an improvement it is possible to update the ControlReg32 component up to 64-bit, so it will look nicer. The actual writing will be in 8-bit chunks anyway. As an alternative, it is possible to arrange the Control Registers inside the ControlReg32, so they occupy consecutive UDB, so a single CY_SET_REG32(...) can be used to populate them. Unfortunately, there is no CY_SET_REG64() instruction, so writing into the registers have to be done in 32-bit chunks anyway.   

If load value is constant, a couple of digital constants can be used instead of ControlReg32's.

The 64-bit demo occupies about 38% of the PLD space and allows for max BUS_CLK or 117 MHz.

All essential components are included into the projects. The KIT-059: annotation component for CY8CKIT-059 PSoC5LP Prototyping Kit  is optional, and can be removed from the schematic.

/odissey1

ShiftReg64_01a_A.pngShiftReg64_01a_UART.png

ShiftReg64_01a_KIT-059.png

ETRO_SSN583
Esteemed Contributor

Update, downloaded that specific lib version, compiled, all set.

 

Regards, Dana.

 

 

 

Trying to compile I keep getting -

 

ETRO_SSN583_0-1623416770164.png

I got the library itself to compile, made sure the dependencies in order,

still keep getting this error. So I did a search for 'KIT_059_v1_0' in that library in the

KIT-059_lib.cylib and in KIT-059_PID_ex_small.cydsn, cant find

it there...

 

Regards, Dana.

 

 

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odissey1
Honored Contributor II

Dana,

I am out of my computer. Meanwhile, I suggest to delete the KIT-059 annotation component from the page - it doesn't do anything, but shows you a picture of the Prototyping kit, as attached above.

For debugging purposes, what Creator version and OS did you use?

/odissey1

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odissey1
Honored Contributor II

Dana,

Attached is a refreshed  project, which contains updated (beta) version of the ControlReg32 component. Apart some cosmetic updates, it corrects the issue that the  Control Value has always defaulted to 0x00. As a result, the Control Value had always be set through API. This issue in now corrected.

The project also shows Cypress component properties Dialog bug, which treats uint32 type as int32. As a result, values over 0x7FFFFFFF are shifted by 1. The bottom line - 32-bit values need to be set by API, and not to rely on the Default Value.

The KIT-059 annotation was also removed from the project. 

/odissey1

ShiftReg64_01b_A.pngShiftReg64_01b_UART.png

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ETRO_SSN583
Esteemed Contributor

Odissey, I tired to add a parameter type, manual seems to indicated

user can roll his own, but it forces me back to using the standard types

thru uint32, even though GNU supports uint64_t

 

So I can build a validator for 64 bit.

 

Am I barking up the wrong tree ?

 

Regards, Dana.

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odissey1
Honored Contributor II

Dana,

I believe that uint32 is largest data type offered by component properties Dialog. Even that option is broken, as it treats it like int32, (at least in Creator 4.0, as I pointed out above).

I suggest to split parameter into two uint32: HI32 and LO32. And check if the value of 0x80000000u is passed correctly to Verilog. I believe, it is not, instead producing 0x80000001u output.

So my solution above was to use two pseudo-32-bit Control Registers, and to assign parameter values at run-time.

    I also wander if other approaches, like using DMA to emulate a Shift Register might work for this application

/odissey1

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ETRO_SSN583
Esteemed Contributor

I am still trying to get the simple to work. Interesting my solution

now with no control regs (but no 64 bit preset capability) winds up 37%

resources, yours just 1% more. I would have thought the extra regs in

your solution would have produced a bigger hit.

 

The approach I am investigating is to enter the preset as string and write the

validator to check and convert to UINT64. I may be nuts but still going to try.

 

I have looked for video example or docs with a little more info on writing

APIs as validators, weird running into the Pearl thing, see this as a need

for newbees like me. I am still wading thru the manual, its probably all there

and I just need to focus....:)

 

Regards, Dana.

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odissey1
Honored Contributor II

Dana,

You may try using built-in "float" type instead of uint64. It works as uint32 substitute in the Properties dialog, but I didn't check for uint64.

I would still use HI32 and LO32 constants instead, as 64-bit word becomes to looooong. 

     I can try to work out the Validator if you explain the constrains. You can use private messaging for that.

/odissey1

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ETRO_SSN583
Esteemed Contributor

I think float does not translate consistently back to a binary value

reliably. Thats why string makes more sense to me or your approach.

 

I will contact you when I get hung up on validator, trying to learn myself

and will need knowledgeable help. Thanks.

 

Regards, Dana.

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