I've started a compent with the UDB editor and dropped in a Count7. When I build the project, the autogenerated Verilog implmentation includes the instantiation below. GREAT!
/* ==================== Count7_1 ==================== */
Count7_v1_0 Count7_1 (
.en(Count7_1_en),
.load(Count7_1_load),
.clock(clock),
.reset(Count7_1_reset),
.cnt(Count7_1_count), <<<Yummy. I want that!
.tc(Count7_1_tc));
defparam Count7_1.EnableSignal = 1;
defparam Count7_1.LoadSignal = 1;
Now I try to use Count7_1_count or Count7_1_count[0] in the Properties/Outputs or Properties/Variables box, and rebuild. KABOOM! I get the following error:
sdb.M0088:Expression "var_1 = Count7_1_count[0]" has an invalid identifier "Count7_1_count".
Page 192 of <PSoC5LP Architecture TRM_001-78426_0C.pdf> shows that <CFGx SC OUT CTL[1:0]> can select {TC,CNT[7:0]} to the horizontal routing block. Why do I get TC but not CNT? Why is a cnt output available on the Cypress/Digital/Utility/Down Counter(7-bit) component?
What's the easiest way to get to the cnt[6:0] output?
