I have a somewhat strange issue with the static analysis. I basically need a 24bit-counter which is driven by an internal clock (MASTER/3). Since it is 24 bits, it needs to be UDB-based, and therefore needs a sync clock. For that I also use an internal clock (MASTER/1). Now I get the warning that there is a clock path between these two clock, and they are not synchronized:
Warning: sta.M0019: Design01_timing.html: Warning-1350: Path(s) exist between clocks Clock_1(routed) and Clock_2, but the clocks are not synchronous to each other: (ClockBlock/dclk_0, \Counter_1:CounterUDB:sC24:counterdp:u2\/ci) (File=D:\dev\psoc\freqmeter\Design01.cydsn\codegentemp\Design01_timing.html)
Warning: sta.M0019: Design01_timing.html: Warning-1366: Setup time violation found in a path from clock ( Clock_2 ) to clock ( Clock_2 ). (File=D:\dev\psoc\freqmeter\Design01.cydsn\codegentemp\Design01_timing.html)
But both clocks are set to 'synced'. This is part of a larger project, but I have reduced it to this simple example - see the attachement.
What is the problem here, and how can I avoid it?
Regarding the maximum frequency: this is strange - for 24bits it is 29MHz, for 32 bit it is 39MHz? (Also, in the 2.10 version of the component it was 30 vs. 25MHz). (and btw: the 2.20 data sheet duplicates the PSoC3 FF implementation data)
And I still think that the sync component should not be needed here. IMHO this is the whole purpose of the clock/count combination is to do exactly what the sync component does: sample the count input on the rising flank of the clock input.
There is some description of how the inputs are handled in the 2.10 data sheet, but it is confusing to me: it talks about many different clocks (clock, component clock, synchronization clock and master_clk), and doesn't talk about how this relates to the clock/count input pair.
(btw: when testing different bit-depths of the counter, the maximum frequency I get for 16 bit is 33.1MHz, for 24bit it is 28.3MHz, for 32bit it is 25.7MHz)