TePh,
From the sequence referred 1, 5, 9... it follows that something in the project consumes 1/4 of the Status cell per each Shift Register added. I suspect it is a Sync component, which consumes exactly 1/4 of the Status cell. So it will take 4 Sync components to fill one Status cell, and 5-th Shift Register will need a second Status Cell. I suspect that implementation of the Shift Register uses one Sync in the Verilog code (or, possibly UDB Clock Enable with Sync=on)
