More a question of curiosity and personal education: Why does the first (5th, 9th, etc..) Shift Register placed on a schematic consume 2 Status Cells? I had assumed up to this point that Status Cells == Status Registers, but there is obviously more to it than that.
Can you please attach your project?
When we tried to reproduce it we are seeing only one status cell consumed per shift register as shown in the image below:
Please let us know the version of the PSOC Creator IDE that you are using.
Shift Registers are not the only component that uses Status Registers. For example, the UART can use 2 to 4 Status Regs (SR) depending on the configuration.
I suspect you are using another component (besides the Shift Registers) that is using one SR. When you add your first Shift Reg, you now add one more SR. When you add two more (2nd and 3rd) Shift Regs, you add two SRs. and so on...
Check you other component's datasheets. It should indicate how many SRs are being used internally to the component.
Ganesh - PSoC 22.214.171.124 on Windows and all components up to date. And yes, with fresh project (target CY8CKIT-059) and nothing more than a Shift Register, I show 2 Status Cells consumed. Add a second, third and fourth Shift Register and the Status Cell count increments by 1. Add a 5th and it's +2, so every 4th one. Control Cells always increment by the specified +1 amount. Let me know if you need any additional info. And FWIW, I just took the time to download CY8CKIT-059 install to a different laptop, 126.96.36.1991 installed and gave me the same results.
Fortunately this project and the PSoC 5LP devices has enough SRs to support my needs, even with the extra consumption. But if it's something that can be resolved, I'd be happy to have a couple of them back. Let me know if there's anything more I can do to assist.
From the sequence referred 1, 5, 9... it follows that something in the project consumes 1/4 of the Status cell per each Shift Register added. I suspect it is a Sync component, which consumes exactly 1/4 of the Status cell. So it will take 4 Sync components to fill one Status cell, and 5-th Shift Register will need a second Status Cell. I suspect that implementation of the Shift Register uses one Sync in the Verilog code (or, possibly UDB Clock Enable with Sync=on)