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PSoC Creator & Designer Software

Anonymous
Not applicable

First!

   

Yeah, I know, an SR latch is pretty lame. Blame Robert, he challenged me to do it (and it was indeed a challenge given my limited mental capacity). Enjoy anyway, but at your own risk, I have no idea what I'm doing. The Verilog synthesizer "cut the loop" and I have no idea what that means...the whole point was for this thing to have feedback and an undefined state when S=R=1. It seems to work properly on my CY8CKIT -050. Someone smarter than me can tell me what it actually synthesized, I have no idea how to check that.

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Esteemed Contributor II

The RS-FF wil always contain a combinatorial loop. This was a warning showing you just to take care. The verilog code you supplied is perfectly right as far as I could see.

   

Congratulations for engraving the first hardware into silicn!

   

 

   

Bob

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Esteemed Contributor

Page 4 - 10 discusses "cut the loop".

   

 

   

http://www.ida.liu.se/~TDDC33/labs/ASIC-IC_Design-for-Test_process_guide.pdf

   

 

   

Generally refers, both in Analog and Digital, opening up a feedback loop.

   

 

   

Regards, Dana.

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