Anonymous
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Aug 08, 2012
08:16 PM
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Aug 08, 2012
08:16 PM
First!
Yeah, I know, an SR latch is pretty lame. Blame Robert, he challenged me to do it (and it was indeed a challenge given my limited mental capacity). Enjoy anyway, but at your own risk, I have no idea what I'm doing. The Verilog synthesizer "cut the loop" and I have no idea what that means...the whole point was for this thing to have feedback and an undefined state when S=R=1. It seems to work properly on my CY8CKIT -050. Someone smarter than me can tell me what it actually synthesized, I have no idea how to check that.
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