PSoC4100S SPCIF interrupt management to write flash row

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ReMa_3807036
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Hi,

I'm following the example in "PSoC 4100S and PSoC 4100S Plus - PSoC 4 Architecture Technical Reference Manual (TRM)" (par.27.7), to write flash avoiding the blocking; infact the erase/write operation in flash required about 12-20ms, and during this time the CPU is stopped there.

The example shows the mode to avoid this blocking, in particular it is necessary to run code in sram (at least the routines used for the scope) also the interrupt service routine for SPC has to be in sram.

In my project (here attached), I was able to move the routine in sram, I define also the SPC interrupt and redirect its vector address, but this interrupt never happens,  I try to read the register CPUSS SYSARG to check the error code, but with Miniprog3 debugger this register seems to be not readable (I see #######... instead of value), but I can access to CPUSS SYSREQ , there I read the last command sent (0x00000007) really with bit31 =0, the command had bit31=1, seems that it becomes 0 due to interrupt management, the question is who, where?.

In the original example is required to have Clock to 48MHz, but the device I'm using CY8C4125AXI-S433 has 24MHz as max value, could be it the problem?

Someone has had similar problems?

Thanks in advance

Renato

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Hi Dheeraj,

here the FW Archive05 with the right setting of IMO to 48MHz.

The problem was the setting of opcodes (0x0000E8B6) to be done by value to register CPUSS_SYSARG, not by pointer as in other cases (really the doc is not so clear about it).

...

/**********************************************************************************

    Set IMO to 48MHz

* Write key1, key2, byte address, and macro sel parameters to SRAM

*********************************************************************************** */

//REG( 0x20000A00 ) = 0x0000E8B6;  //WRONG MODE TO SET IMO to 48MHz

//CPUSS_SYSARG_REG = 0x20000A00;    //WRONG MODE TO SET IMO to 48MHz

//Right mode is to write opcode directely to SYSARG   

REG( CPUSS_SYSARG_REG_ADDR) = 0x0000E8B6;      //PAY ATTENTION Load argument not the pointer

//Write the API opcode = 0x15 to CPUSS_SYSREQ.COMMAND to setup IMO to 48MHz

// register and assert the sysreq bit

CPUSS_SYSREQ_REG = 0x80000015;

...

With the setting of IMO to 48MHz, the writing of flash is performed, and during that time (about 12ms in my check), it is possible to do other things (in the example there is a while loop with "DoOtherUserStuff()" for this scope).

Br

Renato

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