PSoC Warp Verilog: signed reg / signed wire

[RaAl_264636]

Hi,

I'm fighting with a Verilog implementation which should be configurable to work with either signed or unsigned parallel input. The Warp Verilog reference guide states that reg vectors can be signed. For wire vectors, it's not explicitely mentioned that they can't be of signed value.

PSoC Creator throws the error message 'Syntax error at/before reserved symbol 'signed'.' This let me assume that having signed wires is not possible. If this is true, it would be nice if this error message could be more precise about that.

Anyway, if wire vectors can't be signed, how can I solve the problem? I can try to implement it with signed reg vectors, but wouldn't that cost more ressources?

Regards,

Ralf

[odissey1]

I haven't seen signed wires. You have to convert signed input [-128, 127] into the binary offset [0, 255] and work with unsigned wires.

Take a look on Sine/Cosine generator example posted by JLS1, particularly how higher bits are padded to make binary offset values:

http://www.cypress.com/comment/351041#comment-351041 

Can you describe more about the input source and component functionality?

odissey1

[RaAl_264636]

Hi odissey1,

thank you, I'll look into it and check if I can solve my problem based on this.

Regards,

Ralf