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Information on the use of the ADC range/limit interrupt is pretty sparse for PSOC4.2 BLE. Does anyone know how to:
1. Create an interrupt handler that functions e.g reads and clears the appropriate range registers.
2. Initialise the interrupt handler e.g ...startEx(range_handler) or some other mechanism?
Thanks,
Dave
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Thanks for the code sample LinglingG_46,
I have a quick look at the sample and have a couple of questions:
The code:
intr_status = ADC_SAR_Seq_SAR_RANGE_INTR_REG;
if((intr_status & 0x0001) == 1)
Suggests that ADC_SAR_Seq_SAR_RANGE_INTR_REG may have more bits set than just the range bit for the configured channel, is that likely?
Was the opamp buffer purely to manage the output impedance of what may be connected to pin1 and is that necessary if the pin is HiZ analog?
Thanks,
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Suggests that ADC_SAR_Seq_SAR_RANGE_INTR_REG may have more bits set than just the range bit for the configured channel, is that likely?
Yes, more details, please refer to the register TRM: https://www.cypress.com/file/135861/download
Was the opamp buffer purely to manage the output impedance of what may be connected to pin1 and is that necessary if the pin is HiZ analog?
Not necessary.
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Thanks for the help and references LingLingG_46.
A little further information for anyone reading this post:
- The ADC_SAR_IRQ handler handles all the ADC_SAR interrupts (there are 10 interrupt sources see the register TRM reference (linked above), you can use ADC_SAR_Seq_SAR_INTR_CAUSE_REG to work out which one.
- With only the channel_0 low limit interrupt set the interrupt sequence in the handler seems to be an End of Scan (EOS) interrupt first then the next interrupt will be a Range interrupt ORed with an EOS interrupt. This cycle repeats for every range interrupt.