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I am trying to set up a 4-channel communication link between Xilinx Kinetix-7 SerDes as Receiver and Cypress CYP15G0401DXB hotlink II chip as transmitter, the protocol to support is Fibre Channel 1994, but I am having issues on channel bonding and clock correction. It seems that CYP15G0401DXB uses a special 16 word Sync Sequence for channel bonding which doesn't work on Xilinx SerDes Receiver and Xilinx Receiver requires some special characters for clock correction, which the Cypress transmitter couldn't provide in the Fibre channel protocol.
would it be easier for me just to implement clock correction and channel bonding logic by myself in FPGA?
Does anyone have similar exprience and could you share some information on how you solved the issue?
I would suggest to ask Cypress directly, because I have not heard of someone else working on a similar problem. To dos so: at top of this page "Design Support -> Create a Support Case" and ask your question again.