How to not to expand an equation

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Skoe
Level 2
Level 2
10 sign-ins 5 replies posted 5 sign-ins

In a design with combinatorial logic on an PSoc 4 device I run into a placement problem which boils down to the following issue:

An combinatorial enable signal, which is used in several places, like here, p7:

assign enable = x && !y && z;
assign p7 = enable && a && !b && !c

 

is inserted into another term during synthesis and optimization:

Note: Expanding virtual equation for '\FOO_1:enable\' (cost = 2):
\FOO_1:enable\ <= ((not Net_48 and Net_49 and Net_47));

Note: Expanding virtual equation for '\FOO_1:p7\' (cost = 60):
\FOO_1:p7\ <= ((not Net_48 and not Net_38 and not Net_37 and Net_49 and Net_47 and Net_31));

The the digital placement fails with:

W2555: UDB : UDB_0 (PLD : 1) contains 14 data inputs. Maximum allowed 12.

I know that it would fit if the enable signal would go to another PLD and p7 would use enable instead of (not Net_48 and Net_49 and Net_47).

I tried to play with opt_level and placement_force, but these don't seem to help here even though I see they are recognized in the rpt file. However the expansion during synthesis is still done.

Is there a way to avoid this? Something like optimizer settings or explicitly saying that enable must be kept and not expanded into other terms?

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Skoe
Level 2
Level 2
10 sign-ins 5 replies posted 5 sign-ins

Thanks for the heads up! Indeed, I remember that I read that the UDBs are not active in deep sleep and wanted to check if this is only valid for clocked logic, but that's not the case.

Fortunately with juggling with placement_force I could make it fit. So I can leave the core running at 3 MHz and get it for 1 mA, which is sufficient for my application.

PSoc is really a great and flexible platform, I'm happy to work with it and to get to know it better!

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