How to chain clock dividers?

[JoBr_1593366]

I'm trying to learn if I can make a very slow clock without using up UDB/counters, etc.  The PSoC® 3: CY8C34 Family Datasheet says:

Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, master clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.

I can make a Clock component and it will use one divider up to 65536 to produce it, but how do I then route it back through another divider?

[Len_CONSULTRON]

JoBr,

I could not find a way to chain clock components.

I have found low resource clock reduction.

Here's a method to get a clock reduction of 2^(16 + 32).  Using IMO as the source at 3MHz, the resultant output is 10.65nHz.  Is this slow enough?

However the datasheet for the BasicCounter list 35 macrocells used for 32 bits.

Another solution uses a Fixed Function Timer/Counter and 1 macrocell. resultant output is 698.5mHZ

[JoBr_1593366 · Accepted solution]

I think I figured it out:

First Add Design-Wide Clock...

In my case I already had a regular clock at 2 Hz, which I replaced with this. 

So there is a design-wide clock sourced from 100 kHz ILO with 50,000 divider to get 2 Hz. 

Then add a regular clock and use the design-wide clock as its source, and then specify a divider of 600 to get a 5 minute clock.  At first it complained about "Error-1363: Invalid edge values ( 1, -2147483647, 1 )" (whatever that means), but I then found that if I disabled "Sync with BUS_CLK" it accepts the configuration without errors.  Now to test if it actually works...

...

Yes, it works.    Both clocks consistently start with 0 at their outputs, then (if I set the second clock's divider to 30), the second clock stays low until 30 pulses of the first clock, then switches to high.  Then after 15 more pulses, it switches to low again, then another 15 and it switches to high, etc.

If I make a DW clock and feed it to a regular clock, both set to the same frequency, there is a delay before the second clock starts switching, so that's important to keep in mind.  DW clock goes high 4 times before the derived clock starts going high.

[Len_CONSULTRON]

JoBr,

Yes.  If you start with a slow source clock (ILO) you don't need nearly as many divisions to get it to 5 minutes.  Note however that the ILO clock resolution is not highly accurate.  -50%/+100%.  This could mean your 5 minute timer tick could be as short as 2.5 minutes or as long as 10 minutes.

If you want more accuracy +/- 200ppm or better, use a simple fairly inexpensive watch crystal on Pins P15.2 and P15.3.   You can then use XTAL 32K as the source and be within less than 1 sec accuracy.

[JoBr_1593366]

"This could mean your 5 minute timer tick could be as short as 2.5 minutes or as long as 10 minutes."

Yeah I noticed this.  🙂  I don't care, though, it's just a failsafe to power itself off if there's a bug that gets stuck in a loop, etc.

[RodolfoGL]

It seems you are implementing a watchdog timer mechanism. If yes, the PSoC 3 has a hardware watchdog timer. Although you might not be able to achieve the 5 minutes period you want.

[JoBr_1593366]

Similar yes, but it's a bootloader, so the main loop cannot feed the watchdog, it would have to be an interrupt or something, and it's just an emergency timeout in case of a bug anyway.

[JoBr_1593366]

It says "up to 32 bits" so out of curiosity, I tried to chain 4 dividers, and it allows it and works.  Design-Wide clock from 24 MHz IMO, divided by 50000 to 240 Hz, then divided again by 24 to 20 Hz, then divided again by 100 to get 5 second period, then again by 10 to get 50 second period, which I timed with  a stopwatch.  (Anything lower than 0.001 Hz is displayed as "0 Hz")

[Len_CONSULTRON]

JoBr,

Can you share your project with this thread?  Even if it is a minimized version of it.

I'm personally curious how you were able to chain the clock dividers without some macrocells being used.

[JoBr_1593366]

I don't know if it uses additional resources. I'm just configuring everything on the Clocks page:

ILO 100 kHz / 50000 = SLOW_CLK 2 Hz (low accuracy)

IMO 24 MHz / 240 = dwClock_1 100 kHz

dwClock_1 100 kHz / 50000 = dwClock_2 2 Hz (higher accuracy)

dwClock_2 2 Hz / 100 = dwClock_3 0.02 Hz

dwClock_3 0.02 Hz / 10  = dwClock_4 0.002 Hz

But as long as syncing with BUS_CLK is disabled, I can set them all to 65536 and it doesn't complain, even though that would be a period of 24000 years.

[Len_CONSULTRON]

JoBr,

Thanks.   Your latest picture and previous posts connected the dots.   I didn't know this chaining technique was available.   Now I do.

Yes.  The "Nominal Frequency" below 0 Hz is listed as 0 Hz.  I guess you have to calculate it yourself.

Using ILO = 1KHz and 8 DSI_D chaining with the divisors all equaling 65536 should yield a nominal output at the last of the chain to be 10.8 octillion (10.8 x 10e27) years.

Get your stopwatch out to test this idea! NOT!

[JoBr_1593366]

Makes me think of https://www.youtube.com/watch?v=Sd0Roat3CvE