Customer application where he is relying on ARM when power off GPIO will be in HiZ state.
Two cases to this to consider, Power disconnected (switch opens to PSOC Vdd) or power collapses,
such as in a transformer fed simple bridge > regulator PSOC, where PSOC power pin is always "in circuit,
connected".
Ap notes do not discuss this. I stated to customer than when Vdd drops below its min datasheet spec value
all bets are off as to what a GPIO pin looks like. That there is possible charge trapping inside device driving gate
that would have to bleed off to make sure a device, in this case the NMOS side of totem pole, and that could take a
long time.
Question, what is the state of a GPIO pin, and can it be controlled, pre destined, when Vdd drops below operating
datasheet spec value ? I think answer is NO !
Regards, Dana.
