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PSoC Creator & Designer Software

ETRO_SSN583
Esteemed Contributor

Customer application where he is relying on ARM when power off GPIO will be in HiZ state.

 

Two cases to this to consider, Power disconnected (switch opens to PSOC Vdd) or power collapses,

such as in a transformer fed simple bridge > regulator PSOC, where PSOC power pin is always "in circuit,

connected".

 

Ap notes do not discuss this. I stated to customer than when Vdd drops below its min datasheet spec  value

all bets are off as to what a GPIO pin looks like. That there is possible charge trapping inside device driving gate 

that would have to bleed off to make sure a device, in this case the NMOS side of totem pole, and that could take a 

long time.

 

Question, what is the state of a GPIO pin, and can it be controlled, pre destined, when Vdd drops below operating

datasheet spec value ? I think answer is NO !

 

Regards, Dana.

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Len_CONSULTRON
Honored Contributor II

Dana,

Let me take a 'stab' at an answer.

If the GPIO pin in question is near 0V (low) at the time of PSoC VDDD power loss then the pin should remain at or near 0V.   

If the GPIO pin is >VDD/2 at the time of PSoC VDDD power loss, eventually the pin will yield 0V.  However in this case, the GPIO pin MIGHT perform one or more oscillations between low and high until the CPU sees a power off low-voltage reset condition (PRES).

If you need the GPIO pin to be >VDD/2 even when the PSoC is powered off, you may need to have a medium to high value resistor pull-up on the line.  The resistor needs to be a high enough resistance to prevent the latch-up failure condition.   Depending on the PSoC family you're using, they provide an SIO pin which as up to 5.5V protections on-chip to prevent latch-up.

Someone from Infineon might have a better answer than mine.

Len
"Engineering is an Art. The Art of Compromise."
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ETRO_SSN583
Esteemed Contributor

So we can't say, with certainty, with absolute knowledge, what happens to gate

charge on output drivers, N and P MOS, what will happen and when it will happen

(discharge of gate charge). Thats the only conclusion I get.

 

And we can't conclude anything about glitching on  outputs either when power

is out of spec. Sounds like a good ap note is needed that addresses this, especially

where designs are involved in safety and machine reliability. We don't want that 1000A

IGBT driving a 50 HP motor at the wrong time ......

 

Regards, Dana.

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Len_CONSULTRON
Honored Contributor II

Dana,

Understood.   In automotive, the answer is before killing the power to the controller, kill the power source to the IGBT first.  Verify the IGBT is de-powered, then the control can be de-powered safely.   In this scenario even if the controller glitches, the IGBT can't provide any significant power to the motor load.

Len
"Engineering is an Art. The Art of Compromise."
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