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PSoC Creator & Designer Software

doc62
New Contributor II

Hello, I'm creating an application for PSOC PSOC 5 LP using PSOC Creator V4.4

I just finished to address all the build errors of my first verilog file implementing some datapath.

After solving the last error message generated by the fitter now I'm stuck with error message:

Error: fit.M0050: The fitter aborted due to errors, please address all errors and rebuild. (App=cydsfit)

with no other errors nor warnings! How can I proceed?

Thanks

 

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1 Solution
MotooTanaka
Esteemed Contributor

Hi,

I found the report file in the project folder/directory, which is the folder named "ACCDPtest.cydsn"

012-report_file.JPG

If you don't have the report file "ACCDPtest.rpt" in that directory, may be your compiler setting is different from mine. My compiler settings looks like the below.

010-BuildSettings-Compiler-General.JPG

I could even not find "Deleting file .\ACCDPTest.rpt" in the output window.

As above, you might have changed the message output level...

Meantime, please make sure that you are seeing the "Output" tag at the bottom,

instead of "Notice List"

011-Output.JPG

moto

 

View solution in original post

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9 Replies
Len_CONSULTRON
Honored Contributor II

doc,

Are you will to share this project with the forum for others to reproduce the issue?

 

Len
"Engineering is an Art. The Art of Compromise."
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doc62
New Contributor II

Hello Len, thank you for your reply. I extrapolated from my project just the component that seems to be responsible of the issue.

You can find it in the attachment (I hope I did it right). My full project gives the same error.

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Len_CONSULTRON
Honored Contributor II

doc,

Thanks for uploading your project. 

I'm not a Verilog expert.  I was hoping someone with more experience in Verilog would be able to look at your project.

From the format of your .v file it appears to be generated from a .cyudb from a UDB editor.

Here is a very crude observation from someone (me) who is not a Verilog expert.

It appears your Verilog code has no state machines defined.  It appears to have a single-clocked transfer functions of Ave_Range, Ave_Data_0, Ave_Data_1, Ave_Data_2, Ave_Data_3.

This isn't illegal but I wonder if the Warp engine trying to make the datapath connections you are asking for are failing and there is no Verbose message to that effect.

Len
"Engineering is an Art. The Art of Compromise."
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MotooTanaka
Esteemed Contributor

Hi,

I also downloaded and tested your project.

I agree with you about the problem of the error message without error (display).

First I encountered a couple of problems

(1) I got Unable to find component "cy_boot_v5.82" error

  By Updating components using the menu "Project > Update Components..." fixed this.

(2) Seeing the schematic, there is no output connected.

 And in the "Pins" there was no pin assigned.

 Although I'm not sure about PSoC Creator, in may EDA system, unused components will be removed.

But still got the same error.

 

Then I noticed that in the "Output" window, the first line is saying "Deleting file .\ACCDPTest.rpt"

So I located the report file ".rpt" and in the report file, there were error messages 

such as

tovif: ACCDPtest.v: (E100) Too many values (101) for 'pi' of size 8
tovif: ACCDPtest.v: (E100) Too many values (39) for 'pi' of size 8

002-part_of_report_file.JPG

So as you wrote in your later post, I'm afraid that you must find and fix some errors.

And although the PSoC Creator's message in the WorkBench message seems to be insufficient,

may be referencing the report file serves you better.

 

moto

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doc62
New Contributor II

Thank you very much Moto.
I tried to search for the .rpt file without success, I could even not find "Deleting file .\ACCDPTest.rpt" in the output window. Maybe I should set to more verbose Output? How?

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MotooTanaka
Esteemed Contributor

Hi,

I found the report file in the project folder/directory, which is the folder named "ACCDPtest.cydsn"

012-report_file.JPG

If you don't have the report file "ACCDPtest.rpt" in that directory, may be your compiler setting is different from mine. My compiler settings looks like the below.

010-BuildSettings-Compiler-General.JPG

I could even not find "Deleting file .\ACCDPTest.rpt" in the output window.

As above, you might have changed the message output level...

Meantime, please make sure that you are seeing the "Output" tag at the bottom,

instead of "Notice List"

011-Output.JPG

moto

 

View solution in original post

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doc62
New Contributor II

Thank you Len, the component I posted holds just all Datapath I need in my project. There is another component for the State Machine (which is quite big). I checked myself every row of code changing every line that I suspected to be wrong. At some point i must have solved the bug that was giving no verbose message and the builder started to give me new error messages.  I think it was in row 117. I realized I was assigning an output  to a variable instead of the countrary.  At that point the builder started to give me verbous error messages again. There were quite a lot more errors  I'm still debugging in this and other components. I'm an absolute beginner in "Hardware coding" but I don't like to start with  "LED blink" projects. This is my second project with PSOC systems. I believe it is a wonderful family of products but, in my experience, PSOC Creator has an amazing architecture (components drag and drop is fantasic) but has still some little bugs that make me crazy .  Did anybody share my  experience?

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Len_CONSULTRON
Honored Contributor II

doc,

I am also impressed with the PSoC architecture.   I like the ability to create HW state machines to aid in reducing the CPU overhead.

In general, I find if you just drag-n-drop components on the TopDesign, the IDE and support tools work mostly without any issues (assuming that your design can fit in the selected part).

However, I have found when working with the UDB editor there are some issues that can be "worked-around" and do require more design caution and may not have great error or warning messages.

You apparently found this with direct to Verilog design of which I'm not very well acquainted.

Hopefully this post is monitored by Infineon so that they can put the issue you found on a list for future investigation if they chose to improve the toolset.

Len
"Engineering is an Art. The Art of Compromise."
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doc62
New Contributor II

Thank you Moto. In that file there were enough informations to help me focus on the issue. I had to find the mistake myself loosing a lot of time.