ezbe,
Corruption as you described is basically impossible.
Setting up the DMA in essence synchronizes the data transfer to the UART.
If you were performing CPU-only transfers from the UART FIFO to RAM, it is possible to not service the UART fast enough and receive a FIFO overrun error.
Reason #1 - FIFO
There is a 4-byte FIFO on the UART component. As long as you are removing the newly Rx'd byte immediately after it comes in, the FIFO will not get full. You can reliably pull data out of the FIFO's front-end as the newly serialized Rx data in being loaded into the back-end.
Reason #2 - DMA
Create a DMA event to move data from the UART's FIFO to RAM based on "RX FIFO not empty". In most cases it takes at least 10-bit frames to acquire UART data. Therefore, setting up the DMA to transfer the latest acquired Rx Data will only take a few CPU cycles from when it was first available to the FIFO. Whereas, the next Rx data will take 10*<bit_rate> before it is available to load into the FIFO.
Len
"Engineering is an Art. The Art of Compromise."
