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PSoC Creator & Designer Software

ezbe_290006
New Contributor II

hi,

i want to use the DMA of psoc 5 to read from the uart to an array .

my question is :

the UART is asynchronous to my ISR, what will happen if at the exact same time the DMA writes to the array the isr will read from the same address will i receive a corrupted data?

 

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3 Replies
Len_CONSULTRON
Honored Contributor II

ezbe,

Corruption as you described is basically impossible.

Setting up the DMA in essence synchronizes the data transfer to the UART. 

If you were performing CPU-only transfers from the UART FIFO to RAM, it is possible to not service the UART fast enough and receive a FIFO overrun error.

Reason #1 - FIFO

There is a 4-byte FIFO on the UART component.  As long as you are removing the newly Rx'd byte immediately after it comes in, the FIFO will not get full. You can reliably pull data out of the FIFO's front-end as the newly serialized Rx data in being loaded into the back-end.

Reason #2 - DMA

Create a DMA event to move data from the UART's FIFO to RAM based on "RX FIFO not empty".   In most cases it takes at least 10-bit frames to acquire UART data.  Therefore, setting up the DMA to transfer the latest acquired Rx Data will only take a few CPU cycles from when it was first available to the FIFO.  Whereas, the next Rx data will take 10*<bit_rate> before it is available to load into the FIFO.

Len
"Engineering is an Art. The Art of Compromise."
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ezbe_290006
New Contributor II

hi,

thanks for you replay.

i am not talking about fifo overrun,  i am talking about memmory access, if i read from ram address which the DMA is writing to at the same time, what will i read?

(the DMA is not synchronize to the isr)

thanks

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Len_CONSULTRON
Honored Contributor II

ezbe,

I think I understand your description of the CPU reading from the same RAM being written to by the DMA at the same time.  This could be a problem if the UART data rate is fast and the CPU has latency is long.

I'm also assuming that you have only one RAM memory location to DMA the UART Rx data into.

Here's a method to address this issue.

Double-Buffering

Allocate more than one byte for DMA.  For example: Allocate two bytes (data[2]) in RAM for DMA'd UART Rx data.  On the first byte of UART Rx, DMA it to data[0].  On the second byte DMA it to data[1].  On the third byte DMA it to data[0].  An so on...

Connect the ISR for the CPU to process the UART Rx data to the 'nrq' output of the DMA.

Len_CONSULTRON_0-1617884614294.png

The ISR then should then synchronize which of the two bytes to process.

If you'd like to share your project with the thread, we can take a look at it with better suggestions.

 

Len
"Engineering is an Art. The Art of Compromise."
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