Mar 13, 2013
09:27 AM
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Mar 13, 2013
09:27 AM
The counter component does not have the ability to unselect the presence of an Enable. It is always
shown. If enable is tied logically high, always enabled, does clock spec meet 49.2 Mhz for Vdd >= 4.75 V ?
Datasheet a little confusing on this.
Regards, dana.
4 Replies