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PSoC Creator & Designer Software

ETRO_SSN583
Esteemed Contributor

   

 

   

The counter component does not have the ability to unselect the presence of an Enable. It is always

   

shown. If enable is tied logically high, always enabled, does clock spec meet 49.2 Mhz for Vdd >= 4.75 V ?

   

 

   

Datasheet a little confusing on this.

   

 

   

Regards, dana.

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