PSoC Creator & Designer Software

[ETRO_SSN583]

       

The counter component does not have the ability to unselect the presence of an Enable. It is always

   

shown. If enable is tied logically high, always enabled, does clock spec meet 49.2 Mhz for Vdd >= 4.75 V ?

       

Datasheet a little confusing on this.

       

Regards, dana.

[ETRO_SSN583]

29466I is the part of interest.

       

Regards, Dana.

[ETRO_SSN583]

The answer is if enable tied high, higher frequency at 5V applies.

       

Main datasheet, should be reflected in it, conditions that is.

       

Regards, Dana.

[Anonymous]

        Hi Dana-san, Where did the AC specs came from? According to counter data sheet v2.5, Maximum input frequency is 48MHz at VDD=5.0, regardless using of Enable-signal. When I using the counter, It's work well upto 50MHz actually. Happy 29466!   

[ETRO_SSN583]

29466I datasheet in Designer Device Documents. AC specs.

       

Regards, Dana.