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I want to build a simple SR flip-flop that is not synchronized. Simple two NAND gate design you find in basic logic. If I use synthesis optimization I get a lovely *Warning* - "Warning-1361: The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at SR_Feedback1/main_1 --> SR_Feedback1/q" which apparently alters the design for a WARNING.
Looking in the forums, the *fix* is to set synthesis optimization to none, but then the design no longer fits.
So optimization means the synthesizer get to be my mother too?
Solved! Go to Solution.
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This is why the rs ff in the component list is synced to a clock.
Way out could be to use a design where the set signal supersedes the reset signal(or the other way round>).
Bob
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This is why the rs ff in the component list is synced to a clock.
Way out could be to use a design where the set signal supersedes the reset signal(or the other way round>).
Bob