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PSoC 6 MCU

New Contributor

Hi,

My question is about the maximum frequency could cm0+ get up to.

I am now using PLL at 150MHz to run cm4, to achieve that I modified PERI_INV value to 0 in CM0_CLOCK_CTL register so that peripheral divider is now 1. The datasheet says m4 maximum at 150MHz and m0 + is 100MHz. However, when testing with simple LED blinking and measure frequency with a scope, both m4 and m0+ runs at 150MHz . My guess is that the two cores share the same SystemCoreclock global variable and that updates both cores when SystemCoreClockUpdate() called. But is running m0+ at 150MHz possible? Am I measuring something totally wrong that's nor the real clock speed of m0+?

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Employee

Hi,

Peripheral clock, CM0 and CM4 clock are derived from the CLK_HF0. By spec the CM4 is limited to 150MHz and the Peripheral clock and CM0 to 100MHz. But due to the fact, that there is no fractional divider, both Peripheral and CM0+ have to run at 75MHz at max when CM4 is running at 150MHz (divide by 2).

I assume PERI_INV is meant to be PERI_INT_DIV.

In this case you are overclocking the Peripheral clock to 150MHz but the CM0+ should run at 75MHz, as the division is 1+CM0_CLOCK_CTL = 2.

Correct would be PERI_INT_DIV = 1 and CM0_CLOCK_CTL = 0, so all clocks are in spec.

pastedImage_0.png

regards,

Achim

View solution in original post

1 Reply
Employee

Hi,

Peripheral clock, CM0 and CM4 clock are derived from the CLK_HF0. By spec the CM4 is limited to 150MHz and the Peripheral clock and CM0 to 100MHz. But due to the fact, that there is no fractional divider, both Peripheral and CM0+ have to run at 75MHz at max when CM4 is running at 150MHz (divide by 2).

I assume PERI_INV is meant to be PERI_INT_DIV.

In this case you are overclocking the Peripheral clock to 150MHz but the CM0+ should run at 75MHz, as the division is 1+CM0_CLOCK_CTL = 2.

Correct would be PERI_INT_DIV = 1 and CM0_CLOCK_CTL = 0, so all clocks are in spec.

pastedImage_0.png

regards,

Achim

View solution in original post

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