PSoC 6 MCU

I'm working on a design with the PSOC 62 CY8C6245 MCU alongside a CYBT-353027-02 module (our use case requires SDHC communication for eMMC memory), and I'm having some trouble getting a BSP set up to work in this scenario. Is it possible to configure a BSP that uses both of these devices? If not, what's the best way to get those two systems talking to one another so I can incorporate BT in the design?

Hello Community

I am working on a PSoC 6 Project which implements the CY8C6347FMI-BUD53

Programming environment is the ModuxToolBox Version:  2.2.0

Pushbutton connected to P0_4 ( wakeup pin ), PMIC_ENABLE connected to P0_5 (wakeup out).

I want to shut down the VDDD Domain for sleep. only keeping vbackup running for later pushbutton interrupt.

I tested this code.

// VDDD is shutdown at PMIC_ENABLE disabled, and Enter Hibernate.

if (Cy_SysPm_PmicIsOutputEnabled())

{

  Cy_SysPm_PmicUnlock();

  Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_HIGH);

}

resStat = Cy_SysPm_SystemEnterHibernate();

// not reach

if (resStat != CY_SYSPM_SUCCESS) {

   printf("ERR Hibernate. ret:0x%x\r\n", resStat);

}

after that,

Pressing Pushbutton  while PSoC6_MCU is System_hibernate_mode, but pmic_wakup_out :P0[5] is not changed to High,

so and MCU does not return to System_LP_mode .

Hi folks,

I'm working on enabling the backup domain on the PSoC 6. I followed the instructions in this post, and found that the new code generated by PSoC Creator removed a call to Cy_SysLib_ResetBackupDomain() during initialization, as well as some code to disable and enable ILO. I then found that this function's description mentions an "ILO glitch" which can occur when the PSoC is reset due to POR/BOD/XRES while the backup voltage is supplied to the system. 

When I generate code with "vBackup Source" set to VDDD, this function is called, but when I generate code with "vBackup Source" set to "Dedicated supply" it is not. However, the description of this function would seem to imply that the ILO glitch it is meant to address will only occur if the system has a dedicated backup power supply connected to VBACKUP. Could anyone shed light on why this function call is necessary when there is no backup supply? Is there any harm in removing this call if VBACKUP is shorted to VDDD?

Hi：

    In one project,I found tow same named fuction in the same .c file,how the modustollbox design which funtion to be build?

I am working on a design for a device that needs to capture and transmit microphone data over BLE to a custom app, which will record the audio stream to a file. I have been looking at using the PSOC6 as a possible candidate for the design since it has an I2S/PDM block that could read the microphone data. But I have a few questions:

1. I'd like to implement the BLE connection as a Bluetooth serial port to simplify the communications on the app end of things. Are there any code examples showing how to do this?

2. I saw a code example for a microphone recorder that used DMA to transfer the raw microphone data to a FLASH memory chip to be played back. In my application, I don't need to save the audio data directly on the hardware, but instead, transfer it directly to the phone app to be saved there. Is it possible to use DMA to directly transfer the mic data to the Bluetooth serial port and stream it directly?

Thank you,

Jason Owens

Hi all,

We have a CY8CKIT-064S0S2-4343W kit that we're trying to get up and running with the demonstration code that is generated from AWS. I'm following the getting started guide located here https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_psoc64.html and have successfully done everything up to the point of getting working code.

I've managed to build and flash the provided demo application, and the board successfully boots but then halts shortly after with "ERROR: stack overflow" — the attached screenshot shows what is happening. This happened with no WiFi credentials set, I then tried to set WiFi credentials and the error still happened. 

Any help in resolving this issue would be appreciated!

I am interested in designing a solution for measuring TDS (Total Dissolved Solids) in water and sending the data over the 12V power line to the receiving end where the data is displayed.

I remember using a PSoC for power line communication a long time ago before the PSoC PLC version was released.

If I want to combine using a PSoC for both TDS and PLC, which PSoC do you recommend?

Thank You,

Steve

I'm hoping somebody could please explain the pros and cons of running the PSOC 6 BLE stack on CM0 instead of CM4 like all sample code I've seen demonstrates. First of all, is running it on CM0 even possible? It seems to me that the BLE stack is a low load software module that should work equally well on either core. I would love it if somebody could point me to any appropriate (and current!) app notes and/or example projects.

I'm providing BLE programming expertise to a customer. I have only a few months of experience using the PSOC 6 BLE module so the core selection tradeoff is new to me.

Thanks - JJS

Trying to send a GATT notification with a payload of ~256 bytes between two BLE devices at 2Mbps.  If the devices are at a distance where the initial attempt to send the notification fails (for example, if the frame check sequence is ``bad" as indicated by a sniffer), should a packet sniffer show attempts to retransmit the notification occurring with each successive connection event until transmission succeeds (i.e. frame check sequence ``good")?  Is there any situation in which retransmission of a failed (i.e. unacknowledged) GATT notification does not occur during the very next device connection event (connection interval currently set to ~25ms), and if so, is there any firmware setting to control this time to retransmit? 

The CY8CPROTO-063-BLE board is being used with hibernate and periodic alarms to save system power.  The RTC is producing the expected alarms and the hibernate control is working properly.  There is an external PMIC with an enable input to turn it on and off to generate the 3.3V input for the VDD .  A supercap is attached to VBACKUP  and R29 is removed on the board.  When the unit is also powered from the KipProg3 adapter (via VTARG) it works as intended, hibernating and waking up periodically.  However, When the KitProg3 is unpowered and the external power is only applied into the PMIC, it never gets out of hibernation.

The problem is that pin P0.5 is not being controlled by the hibernate logic as needed.  The PMIC enable (active high) is pulled high by a weak pull-up resistor for when the PSoC 6 is not yet powered or not yet in control ( P0.5 assumed high impedance).  When hibernate mode is started, P0.5 should be pulled low by the PmicEnableOutput and when it goes out of hibernate, it should be pulled high to turn the external PMIC on.   This is not happening.

In response to the forum question "PSoC 6 PMIC Control deep sleep best practise", GaneshD_41 replied suggesting control that is built into the following code:

Cy_SysPm_SetHibWakeupSource( CY_SYSPM_HIBALARM // Wake-up source for RTC alarm

                                                         | CY_SYSPM_HIBPIN1_LOW // Wake-up source for Pin1 input low

                                                         );

  Cy_SysPm_PmicUnlock();                          // Unlock in case locked

//NU   Cy_SysPm_PmicEnable();                // enable Pmic control

  Cy_SysPm_PmicEnableOutput();                // enable P0.5 output control

  Cy_SysPm_PmicLock();                          // Lock again but why?

// Configure the PMIC controller output pin to be active logic low

// after the PMIC is disabled.

//     Note: I do not understand the above comment

  Cy_GPIO_SetDrivemode(P0_5_PORT, P0_5_PIN, CY_GPIO_DM_STRONG_IN_OFF);      //  What does this do?

  Cy_GPIO_Clr(P0_5_PORT, P0_5_PIN);                                                                                 // What does this do?

  if ( Cy_SysPm_PmicIsOutputEnabled() )                // It was just enabled above; so why check?

    {

    Cy_SysPm_PmicUnlock();

    Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW);           // what does this do?

    }

// Prepare the device for system Hibernate

  if ( Cy_SysPm_SystemEnterHibernate() != CY_SYSPM_SUCCESS )

    {

        /* System did not enter Hibernate mode because a registered

        *  Hibernate "check ready" callback returned a "not success" status

        */

    printf(" Hibernate failed\r\n\n");

    Cy_SysLib_Delay(1000); // wait for output

    failed= 1;

    }

The above code was put into the project; yet P0.5 still does not have any output; it always stays low.

Are there any suggestions as to properly controlling the P0.5 pin while going into and out of hibernation?