I am working with the CYBLE-416045-02 chip (with CY8CPROTO-063-BLE KIT) but i am declaring a function in my .h file as the following:
uint8_t WriteCommandPacket(uint16_t cmd);
and the user can send differents commands:
#define CMD_WATER (0x3608)
#define CMD_ALCOHOL (0x3615)
#define CMD_STOP_MEASUREMENT (0x3FF9)
#define CMD_SOFT_RESET (0x0006)
#define CMD_READ_I (0x367C)
#define CMD_READ_II (0xE102)
it is why i am using the uint16_t type to send this command. But the PSoC Creattor 4.4 is telling me the following error:
masterI2C.h:68:9: error: conflicting types for 'WriteCommandPacket'
uint8_t WriteCommandPacket(uint16_t cmd);
The strage thing that i can use this type inside of the functions
Can someone help me out?
Is there a possibility to have two or more memory slots in XIP mode without switching between them manualy?
Now it is only possible to manually select QSPI slave, for example using this sequence:
cyhal_qspi_init(&qspi_psram_obj, QSPI_IO0, QSPI_IO1, QSPI_IO2, QSPI_IO3, NC, NC,NC, NC, QSPI_CLK, PSRAM_SSEL, QSPI_FREQ, 0);
/*Entering XIP mode and working with external PSRAM on slot 0...*/
/*Entering XIP mode and working with external FLASH on slot 1...*/
I am testing the gpio output speed with CY8CKIT-062-WIFI-BT.
I attached the source code based on the Modus Toolbox being tested.
The datasheet says that maximum GPIO speed is 100MHz, but it is measured around 10MHz.
Is there any way to make the output faster?
Thanks and Regards.
I have a problem running the example code
When I run the code, I have a problem like the picture below.
I would like to know how to solve this problem.
- tool : PSoC creator 4.4, mobile CySmart app
- PDL Version : 3.1.4
- mcu : CY8C6347BZI-BLD43
I am testing with CY8CKIT-062-WIFI-BT.
Threre is an emWIN_TFT_FreeRTOS example, but the bitmap image is displayed slowly.
I'm not sure if it's the effect of RTOS, but is there an example that the bitmap image is output quickly?
Dear Cypress Customer service,
Good morning. I'm developing an application for the aforementioned PSoC 6 board, and I need to include a OTA update. Right now, the project makes use of both CPUs of the board (CM0 as well as CM4). I know the CM0 is intended for security uses and encryption, but I need it to do some other things for my project. In this regard, a OTA update should update not only the CM4 's firmware, but also the CM0 CPU.
My question is: is this permitted by the board and the APIs ? If so, my intention would be to set up a HTTPS server to distribute the firmware. How should I set it up to correctly upgrade both CPUs ? Does it mean that I need to distribute 2 different firmwares, one for the CM0 and one for the CM4 ? How should I send the two segments of code ?
Thanks in advance,
Best regards.Show Less
Hi, I am trying to wrap my head around a potential smartio use:
Goal: Deterministic cycling between three GPIO signals that control isolated FETs to toggle between three voltage levels on *one* output pin. To avoid shorts, only one signal may be high, and a dead time between switching would be helpful. In the end I'd like to have a function that enables the smartio voltage cycling like cycle_voltage(count,ontime,deadtime);
Signal pins: SIG_GND, SIG_MID, SIG_HIGH -> controlling the external 0V, 75V, 135V switching in my application:
SIG_HIGH=1 ________ 135V
SIG_LOW=1 _______| | ______... 75V
| | |
SIG_GND=1 ____| |______ | 0V
Desired toggle behavior: 100-500uS signal high, then 0-1uS dead time, then signal high for next SIG_ pin.
- I want to 1) cycle and 2) control signal high time for each signal and dead time from firmware. How do I think of this problem in terms of Chip inputs, clocks and perhaps chained LUTs?
- Can I link the SAR ADC's EOS trigger to start the smartio cycling?
- Alternatively, would it be possible in smartio to start the ADC on the first voltage cycling and snapshot scan every X cycles?
Hi there! Hope you're doing well. I'm new to the whole Psoc 6 environment.
I am currently working on a project that requires me to transfer data acquired from the ADC and send it to an ESP32 via BLE.
Till now I have finished the ADC part. And have done a lot of examples on the BLE (Glucose meter, Heart rate monitor, Thermometer...).
I am now stuck making a BLE server that works. I am trying to use the CE222046_GATT_Out example as previous forum responders have suggested, in order to create a custom service, but I am facing the following issue:
- After connecting to the GATT Out BLE server with NRF connect, I am getting disconnected when I try to enable notifications from the client side via the NRF connect app.
Also some important info:
- The CE222046_GATT_Out example is being used (unedited).
- I am using the CYBLE-416045-02 Psoc 6 prototyping board.
- I am using Psoc creator.
Can someone tell me what am I missing? It's been a while I'm stuck at this stage.
Thank you for your support 🙂Show Less
I have a project using PSoC63 in which the Vdd (and Vdda) varies from 2.1 to 2.5 V. I am using the Scanning SAR ADC as follows:
It appears that, with a constant input voltage, as Vdd (Vdda) increases, ADC readings increase somewhat. I don't have actual numbers - this is simply a consistent pattern that I have observed.
Has anyone else seen this behavior? If so, do you have a fix?
Our SW development shall be done on CY8CKIT-062S2-43012 and we intend to demonstrate it on standalone CY8CMOD-062-43012 module i.e. no additional carrier board but only power supply from battery (currently we are not using any of the module peripheral buses)
1. Correct me if I wrong but from the schematics of both module and pioneer kit, we understand that both 3.6V (VBAT), 1.8V (VDDIO) and 3.3V (VDD) should be supplied to module?
2. For uploading new FW to CY8CMOD-062-43012 do we must use physical connectors (SWD / JTAG) or the default factory FW includes OTA capability?
Thanks in advance
I think the device with the most UDB's has the most resources for implementing verilog- would that be Psoc 5LP ? It seems Psoc 6 devices don't use much in the way of UDB's from what I see in one of the datasheets. Is that a correct assessment?Show Less