PSoC™ 6 Forum Discussions

Hello, I'm trying to use PSoC 62s4 pioneer kit with PSoC creator, and it isn't work. I installed all programs, and I have made all the update, but nothing.

By device manger, seems that the port is ok. 

And the "Program" function is working very slow!!!

Using MTB 3.0, starting from the Dual-CPU_IPC_Semaphore example, I am trying to implement some codes in CM0+. However, during compilation there is an error stating that my flash memory region is overflow. Please advise how can I make the memory adjustment. Thanks!

Compile Output:

Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 203 file(s)
Linking output file proj_cm0p.elf
c:/users/XXXXXX/modustoolbox/tools_3.0/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: C:/Users/XXXXXX/mtw3/Dual-CPU_IPC_Semaphore/proj_cm0p/build/APP_CY8CPROTO-063-BLE/Debug/proj_cm0p.elf section `.text' will not fit in region `flash'
c:/users/XXXXXX/modustoolbox/tools_3.0/gcc/bin/../lib/gcc/arm-none-eabi/10.3.1/../../../../arm-none-eabi/bin/ld.exe: region `flash' overflowed by 21660 bytes
collect2.exe: error: ld returned 1 exit status
make[4]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/build.mk:435: C:/Users/XXXXXX/mtw3/Dual-CPU_IPC_Semaphore/proj_cm0p/build/APP_CY8CPROTO-063-BLE/Debug/proj_cm0p.elf] Error 1
make[3]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/main.mk:376: secondstage_build] Error 2
make[2]: *** [C:/Users/XXXXXX/ModusToolbox/tools_3.0//make/application.mk:72: build] Error 2
make[1]: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/build.mk:314: build_application_bootstrap] Error 2
make: *** [../../mtb_shared/core-make/release-v3.0.0/make/core/main.mk:376: secondstage_build] Error 2
"C:/Users/XXXXXX/ModusToolbox/tools_3.0/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/XXXXXX/ModusToolbox/tools_3.0 CY_IDE_BT_TOOLS_DIR= -j8 all" terminated with exit code 2. Build might be incomplete.

Regards,

Gary

when I add this commponent to my design I got this error

Generated_Source\PSoC6/VDAC.h:23:28: fatal error: ctdac/cy_ctdac.h: No such file or directory

Hello.
I'm using CY8C6136FDI-F42 & Modus v2.4.

To implement the DFU function in PSoC61, I refer to the Basic Device Firmware Upgrade example of CY8CKIT-062-WIFI-BT.
Since PSoC61 is single core, I removed the M0 related part from the linker script file (dfu_cm4_app0.ld).
I also modified the memory address in the script file, but it doesn't work properly.
I am attaching the project file I tested, so please check it.

Thanks and Regards,
YS

CE222802 uses AES for encryption/decryption by using the crypto engine.
Does the crypto engine library require a Cryptographic Accelerator?

Not all PSoC 6 devices contain the Crypto Accelerator.

Greg

Is it possibile use an SD card via SDIO with a Psoc6 without SD Host Controller dedicated?

I supposed is possible as like use connectivity module via SDIO for wifi, but libraries lack of a SD Host Driver...

An SD Host Driver will be provided in future?

I'm tryng to adapt this example

mtb-example-psoc6-filesystem-emfile-freertos

and to add the hardware layer for SDIO, anyone has already try this solution and want to share the code?

@Infineon_Team 

Hello!

I have a CY8CPROTO-062-4343W board and a 4x4 matrix keypad connected to it according to the matrix below.

But I don't understand how to use it. I can't find any guide on the internet how it works.

My first thought was that I need to initialize the pin, for example

Cy_GPIO_Pin_FastInit(P13_5_PORT, P13_5_NUM, CY_GPIO_DM_PULLUP, 1UL, P13_5_GPIO);
Cy_GPIO_Pin_FastInit(P13_0_PORT, P13_0_NUM, CY_GPIO_DM_PULLUP, 1UL, P13_0_GPIO);

Then check if both of them are '1' do something

if((1UL == Cy_GPIO_Read(P13_0_PORT, P13_0_NUM)) && (1UL == Cy_GPIO_Read(P13_5_PORT, P13_5_NUM)))
{
            printf("1\r\n");
}

But this doesn't work, P13_0 and P13_5 is always '1' regardless of the button '1' is pressed or not.

Given a project where a bootloader and an application occupy different regions of the same address space. The existing Linker scripts can be edited to relocate one of the projects. What is the process to debug one of the projects while the other one stays resident in flash?

When the debug session starts with one of the projects, ModusToolbox erases the entire flash address space so the other project disappears from flash. The ability to debug one application while the other stays in flash is vital to how we do bootloaders. The question is: How can a debugging session be started for a project and have the ModusToolbox tell the debugger to only erase the portion of flash that the application is going to occupy and leave the rest intact? (Note we use Segger JLink debuggers)

Greg

Another elementary question:  Are the atomic functions like atomic_exchange() and atomic_flag_test_and_set() dual-core-safe on the PSoC 6?  I'd expect these to work, but there's not much shared memory discussion.