PSoC™ 6 Forum Discussions

Hello Infineon Community,

I have been working with PSoC 6-based CY8C6244LQQ-S4D92 microcontroller. The issue with this MCU is happening when I am trying to read the state of the P12.6 and P12.7 pins, every time when I read the state of these 2 pins, it's always low if it is connected to the 3.3V supply also. Otherwise, other input pins are working fine, just these two pins are showing some issues. I tried to change the mode of these two pins also but didn't succeed. 

Please help me with this issue.

Thanks & Regards,
Vivek Karna

a few years back I did this, but I've lost track of where I got the utility.  I need to put an image on the display.  From my recollection I had to take the image (jpg I think) and run it through a utility that the e-ink manufacturer sent me.  I got that information from you folks.  Could you provide me the contact information or website for the e-ink manufacturer so I can get this utility again?  Many thanks.

Steve

I wish to upload the written code into my Psoc6 through UART and it should load into bootloader and load the program .

How can i do so?

Hi ,

I am working on the PSOC62 free-running WDT , I followed the example in the following link to use the PDL as i am working on the CM0.

https://github.com/Infineon/Code-Examples-for-the-ModusToolbox-PSoC-6-SDK/blob/mt1.1/CE220060_PSoC6_WatchdogTimer/Source/main.c

The interrupt part of the sample works fine , but we when I invoke the WDT_RESET_DEMO  the unit does not trigger a reset as per the documentation . In the WDT_RESET_DEMO  mode the code does not use the interrupt ISR to do anything , as i understand it in the background after it has had 2 un handled interrupts  on the 3rd it should do a reset . This does not happen . I have changed the Cy_WDT_SetMatch(0); value between 0 and 32000 to give me 1 second triggers but it also does not change it .

I also would like to reset the WDT counter via my system tick , according to the documentation this cannot be done while the WDT is enabled . So it means every 100ms or so i need to disable the WDT , clear the counter , and re enable it . if the system should go into a freez state in this routine the WDT wont reset either as it is now disabled which is a problem.

Using the Cy_WDT_ClearWatchdog(void) to reset the watchdog seems a bit redundant as it only calls the Cy_WDT_ClearInterrupt(void) function which feel a wasted process time . The question here though is , what does it mean by calling this clear interupt flag that the watchdog resets according to the documentation, does it also reset the counter value?

" The WDT_MATCH bit of the SRSS_INTR register is set
whenever a WDT match interrupt occurs. This interrupt must
be cleared by writing a ‘1’ to the same bit. Clearing the
interrupt resets the watchdog. "

I tried adding this to the systick code to clear  the watchdog every 100ms , it does nothing and in the interrupt mode the watchdog ISR still kicks in.

What is the correct way to clear and reset in software the watchdog to make sure the interrupt or watchdog in reset mode does not fire ?

Attached is the Timer codes C and H files for review , this runs on the PSOC 6 Cy8c6247 cm0 is set to 100Mhz

Any assistance is welcome .

Regards

C

Hi,

I am trying to integrate a bootloader into my project and started with the "MCUboot-Based Basic Bootloader". However, I encountered an issue during the compilation process and discovered that adding extra libraries was causing the break.

I have followed these steps so far:

1. Created the application "CY8CEVAL-062S2-MUR-43439M2/MCUboot-Based Basic Bootloader"
2. Added the "wifi-mw-core" library to the "blinky_cm4" project
3. Modified the "blinky_cm4" Makefile by adding the following lines (as per the wifi-mw-core Readme):

COMPONENTS=FREERTOS LWIP MBEDTLS

DEFINES+=MBEDTLS_USER_CONFIG_FILE='"mbedtls_user_config.h"'
DEFINES+=CYBSP_WIFI_CAPABLE
DEFINES+=CY_RTOS_AWARE

I received the following errors in the log (attached):

• "#error "MBEDTLS_SHA256_C defined without MBEDTLS_SHA224_C"

I attempted to resolve this by adding the definition "MBEDTLS_SHA224_C" to the Makefile, but this resulted in a new set of errors, specifically "error:

• 'MBEDTLS_ERR_AES_HW_ACCEL_FAILED' undeclared (first use in this function)".

Every other attempt I made only produced different errors.

Can you provide assistance with this issue?

I am trying to create the bootloader build in example, but its giving me this error.

ERROR:Failed to export the "MCUboot_based_Basic_Bootloader_for_PSoC_61" application to Eclipse IDE for ModusToolbox™.

I am using the MODUS IDE because my PSOC 62 kit / is not available in PSOC Creator.

I am trying to chain 2 DMA components together using the HAL driver.

My first DMA component triggers off a digital input pins rising edge, and that works as expected.

The second DMA component should trigger when the first DMA completes, but when I setup the source, I get an error.

Based on the documentation, I can't figure out what I am doing wrong.

Error Code is the following: Module: 0x100 Code: 0xD01 Type: 0x02

Code:

cyhal_source_t mem_trigger_src;

rslt = cyhal_dma_enable_output(&dma_ch[0], CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS, &mem_trigger_src);
if(rslt != CY_RSLT_SUCCESS)
{
    printf("Error! [%d] {%s: %d}\r\n", rslt, __FILE__, __LINE__);
}

result_dec.raw = cyhal_dma_connect_digital(&dma_ch[1], mem_trigger_src, CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST);
if(result_dec.raw != CY_RSLT_SUCCESS)
{
    printf("Error! [%d : %d : %d] {%s: %d}\r\n", result_dec.module, 
        result_dec.code, result_dec.type , __FILE__, __LINE__);
}

So, the call to create create the output on ch[0] works, but when I try to link that output into ch[1], I get the error.

This is very similar to how I configured ch[0] with a digital input pin, but it worked as expected.

Hi Team, 

I'm working on a use case where I have to run MQTT, HTTPs applications on the CM0p core of my PSoC 6 (2M part). I see that the code examples on github.com/Infineon by default run on the CM4 core after the CM0p goes to sleep. I am aware of a Makefile variable called CORE=CM0p but is that enough to successfully build and run a code example (obviously, after the linker script updates to provide sufficient memory for the code coming on the CM0p)? Further, I am also concerned about the code space - if it is possible to fit this into <1M flash (or <512K of flash excluding the 43xxx firmware). like https://github.com/Infineon/mtb-example-wifi-https-server or https://github.com/Infineon/mtb-example-wifi-mqtt-client?

Request you to link me to the sufficient resources to help my use case.

Regards,

Varun Kaushik

I am using v3.0 tools and visual studio code. This is more of a bug report but also a reference for anyone hitting this problem themselves.

I have a custom board with CY8C6244AZI-S4D93 with an external 12Mhz (12000000hz) oscillator going into P0[0]. This is the source signal for PLL which is 150Mhz.

I am running a dual core software app with CM0 and CM4 cores. CM0 does the initialization of peripherals and CM4 runs the main application.

Both CM0 and CM4 have an infinite while loop.

Problem is that when CM0 initializes the external clock frequency with Cy_SysClk_ExtSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ) this doesnt propagate to the CM4 core.

This causes timing error with the various delay functions.

This is verified by calling Cy_SysClk_ExtClkGetFrequency() in both CM0 and CM4 main loops.

In the CM0 it correctly returns 12000000, in CM4 it returns 0. This causes other things to break down such as Cy_SysClk_PllGetFrequency(1) from CM4.

My workaround is to call Cy_SysClk_ExtClkSetFrequency(12000000) as first line of the CM4 app.

This seems like an odd workaround though, since it works correctly when using the IMO.

Either im doing something wrong or the software doesnt account for an ExtClk properly when initializing using the default initializers.