PSoC™ 6 Forum Discussions
Hi all,
I want to use freeRTOS in both cores but it uses the HAL. The PSoC™ 6 MCU: Dual-CPU empty application template says:
The Infineon HAL is not yet designed to run simultaneously on CM0+ and CM4 CPU. Because the proj_cm4 already uses HAL, proj_cm0p should only use PDL APIs.
Is this a problem if using Local git where each core gets a different copy of the HAL? if so, when will this issue be resolved.
Thanks
Show LessHello I designed in the psoc 5 part cy8c5468 QFN68 a few years ago now unavailable. So we bought a batch of a new psco 6 parts to maybe (hopefully replace it) CY8C6144LQI-S4F92. The problem is when I load up my project psoc creator 4.4 the new part is not listed in the device selector list? So I am unable to use it since I can't compile it. How can I get the part on the device list? Thanks.
Show LessAfter updating my project I cannot debug or program it anymore. My project was single core, I updated it to dual core and now the launches on quick panel are not working anymore.
I tried to re-generate the launches, erase all ".project" and ".cproject" (root, CM0 and CM4) and create again using "make eclipse" but nothing worked.
It shows this error:
This the MTB version MTB 3.0.0 build 2749
the command "make program" works, so I believe the issue is on Eclipse IDE.
thank you ,
Magnus
Show LessI have a project using a CY8C6x4 processor (CY8C6247FDI-D32). We have a requirement to service an interrupt on the M4 core at a very high rate (~ every 640us). We also have a requirement to write to flash memory using the M0 core while this interrupt is running. The M0 and M4 cores are running from flash in sector U1 (0x10040000) and the flash being written is U3 (0x100C0000). Below are a bunch of questions related to writing to flash using "partial blocking" methods.
Looking at the PSoC Peripheral Driver Library Flash Section (link) you can use partial blocking methods to try to keep the "non-flashing" core running while doing a flash erase and a flash write. The documentation has Figure 1 which shows some general timing for the StartErase() + StartProgram() method and the StartWrite() method. I have tried both and it looks like both processors get "locked" for a period of time.
Figure 1 has a Legend that shows "Available to read from flash", "Busy with SRM code (CM0+)", and "Blocking-out SRAM". I can figure out what (and see from my traces) what the first two mean. What I don't understand is what does "Blocking-out in SRAM" mean? Does this mean the processor can't execute from SRAM? Also what are the implications of this time period?
I'm trying to get something useful done on the M4 during the "Blocking-out in SRAM" period. From what I can see from traces I have collected is that there isn't much the M4 can do while the M0 is "starting the erase" and "starting the program". The code that I'm running is not getting interrupts during this period. So are both processors blocking in an NMI interrupt? Are interrupts disabled on both processors?
I understand that the M0 is tied up working with SROM and IPC during these times. I also understand that at least on the M0 a critical section cannot be entered. Is that true for the M4 as well? It the M4 locked up on IPC during these times as well?
I'm wondering if I can execute SRAM code on the M4 during this "Blocking-out in SRAM", but it isn't clear to me what blocking-out means. Also I'm not sure why I can't use Flash during this time since the sectors I'm using should be isolated. I have dug into the CY code that is interfacing with the SROM/IPC and it is running in SRAM (so that it is not using the flash or the flash cache).
Any help on this would be greatly appreciated and I suspect others would like to have a better understanding of what is going on while the SROM code is executing.
Best Regards,
Lenny
Dears,
based on USB Audio Device (FreeRTOS) demo I have more question regarding clock settings. I create rather new thread.
I am using PSOC6 (on CY8CPROTO-062-4343W kit). I would like to change CM4 clock to 150 MHz, because I need to speedup CM4 core. But I have problem with CLK_PERI which is used also to generate PWM
PWM setup:
cyhal_pwm_t mclk_pwm;
cyhal_pwm_init(&mclk_pwm, (cyhal_gpio_t) P5_0, NULL);
cyhal_pwm_set_duty_cycle(&mclk_pwm, 50.0f, 18432);
cyhal_pwm_start(&mclk_pwm);
this is MCLK pin for I2S audio and must be synchronized with I2S audio LRCLK
I am able to set 150MHz for M4 code using PLL1 - to generate 150MHz clock and route this to CLK_HF0 from CLK_PATH2, CLK_PERI (divider 2) -> 75Mhz. as shown here.
But PWM now is not synchronized with I2S Audio clock LRCLK
Is there option to generate PWM from another source then CLK_PERI so that this two clocks could be synchronized and CM4 speed could be independent ? Can I used TCPWM? or another block as I normally use in PSOC Creator...
Thanks in advance, regards
Radim
But I would like to have CLK_HF0 independent on ext crystal to be able to run core M4 for 150 MHz
Show LessHello all,
I recently switched from PsocCreator to ModusToolbox. Now I wanted to create an I2C master via the Device Configurator. But I do not understand the procedure. In the examples only the configuration is shown in the code but I don't want to have any settings twice. In addition, I would like to use libraries for sensors and not have everything in the main function. Is there an example how to set up I2C master via Device Configurator, initialize it in the main and use it in an additional file?
Greetings,
Moritz
root@ORU3668_MAIN:~# tpm2_nvdefine -Q 1024 -C o -s 788 -a "ownerread|policywrite|ownerwrite" > tmp.txt
WARNING:esys:../tpm2-tss-3.0.3/src/tss2-esys/api/Esys_NV_DefineSpace.c:337:Esys_NV_DefineSpace_Finish() Received TPM Error
ERROR:esys:../tpm2-tss-3.0.3/src/tss2-esys/api/Esys_NV_DefineSpace.c:122:Esys_NV_DefineSpace() Esys Finish ErrorCode (0x000009a2)
ERROR: Failed to define NV area at index 0x1000400
ERROR: Esys_NV_DefineSpace(0x9A2) - tpm:session(1):authorization failure without DA implications
ERROR: Failed to create NV index 0x1000400.
ERROR: Unable to run tpm2_nvdefine
Hi all,
I created an empty dual core project and I noticed that if I use Cy_SysLib_Delay(500) in both cm0p and cm4 cores to blink LEDs the cm0p code makes its LED blink with the expected 500ms delay but the cm4 code blinks its LED really fast ... way faster than 500ms. If I put cm0p to sleep then the cm4 code blinks as expected (using ECO).
This behavior only happens with the External Crystal Oscillator (ECO) selected for PATH_MUX0. I have a 20 MHz crystal (and caps to GND) connected to pins P12[6] and P12[7]. Cy_SysLib_Delay(..) works fine if I select 8-MHz internal main oscillator (IMO) for PATH_MUX0.
Any ideas what could be the problem?
Thanks.
Show LessPWM does not work if I use the pin P0_0 in below code, it gives fault as soon as I start the timer. If I use pin P0_1 it works.
Any help will be appreciable.
cyhal_pwm_t pwm_obj;
rslt = cyhal_pwm_init(&pwm_obj, P2_3,NULL);
rslt = cyhal_pwm_set_duty_cycle(&pwm_obj,50,1000);
rslt = cyhal_pwm_start(&pwm_obj);
Show Less