PSoC™ 6 Forum Discussions
I need to add a proximity sensor in the black identification part of the photo to realize proximity sensing. The wire on the film is made of carbon film or silver wire connected to the gold finger at the upper right corner, the gold finger connected to the PCB hard board, and the IC placed on the PCB. What are the requirements for this length of wiring?
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Hello friends!
I am referencing the ADC_basic example of Modus Toolbox to see how to read the ADC, I wonder how when I attach my sensor, the ADC will read the value and convert the voltage value read from the sensor. turned into a percentage value!
Thanks!
Show LessI have an application where a SPI based external ADC is used (using ModbusToolbox for development), using the HAL libraries for SPI interface.
The application works fine, until I add LittleFS library to store files/data to a QSPI based serial flash.
The ADC SPI tranfer calls seem to be stuck in the transfer_async where it is waiting for the interrupt.
It appears that LittleFS library (or underlying serial-flash) library might be conflicting with the SPI calls.
My issues seems to be similar to this ticket, but I don't know where to look for conflicting interrupt handlers.
Any suggestions are welcome.
I am trying to run a gesture classification demo on the CY8CKIT-062S2-43012 kit. I am following the steps described in https://github.com/Infineon/mtb-example-ml-gesture-classification.
But as try to import the example using New Application link in the Quick Panel I run into the below error and can not download the example. I have tried both methods described in the https://community.infineon.com/t5/Code-Examples/ModusToolbox-URL-Modifier/td-p/366015 thread but still running into the same issue.
Loading the manifest data
Found environment variable CyRemoteManifestOverride=https://raw.githubusercontent.com/Infineon/mtb-super-manifest/v2.X/mtb-super-manifest-fv2.xml
Loading super manfiest files from all sources
Processing manifest pack file 'C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifest.xml'
Downloading super manifest file 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifest.xml'
Getting manifests from remote and/or local sources
Processing system manifest 'https://raw.githubusercontent.com/Infineon/mtb-super-manifest/v2.X/mtb-super-manifest-fv2.xml'
Downloading super manifest file 'https://raw.githubusercontent.com/Infineon/mtb-super-manifest/v2.X/mtb-super-manifest-fv2.xml'
Finished loading super manifest files from all sources
Finished download of file 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifest.xml'
Starting to parse super manifest with URL 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifest.xml'
Finished parsing super manifest with URL 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifest.xml'
Downloading manifest file 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifests/mtb-ml-ce-manifest.xml'
Finished download of file 'https://raw.githubusercontent.com/Infineon/mtb-super-manifest/v2.X/mtb-super-manifest-fv2.xml'
Finished download of file 'file:///C:/Infineon/Tools/ModusToolbox/packs/ModusToolbox-Machine-Learning-Pack/manifests/mtb-ml-ce-manifest.xml'
Finished loading the manifest data (42454 ms)
Loading the device db
INFO:Using the executable path for the tools directory.
WARNING:Error downloading 'https://raw.githubusercontent.com/Infineon/mtb-super-manifest/v2.X/mtb-super-manifest-fv2.xml' -- Connection timed out
INFO:No device-db assets found in manifest
0 error(s), 1 warning(s
git bash config after modifying the URL as suggested.
core.editor="C:\\Program Files (x86)\\Notepad++\\notepad++.exe" -multiInst -notabbar -nosession -noPlugin
pull.rebase=false
credential.helper=manager
credential.https://dev.azure.com.usehttppath=true
init.defaultbranch=master
url.https://ghproxy.com/https://github.com.insteadof=https://github.com
Let me know if I am missing something.
Show LessHi all,
I am using the PSoC 6 cy8ckit-064b0s2-4343w . I attempted to construct a UART interrupt in Modustoolbox (version 3.0)using SCB blocks without FreeRTOS, and the hardware interrupt happened at that time. However, when I implemented the same code again with FreeRTOS(v10.4.302), I did not encounter a hardware interrupt since FreeRTOS does not call the interrupt function while transmitting.
The PDL(v3.2.0) API's used:
For configuration:
(void) Cy_SCB_UART_Init(SCB5, &uartConfig, &uartContext)
Cy_GPIO_SetHSIOM(UART_PORT, UART_RX_NUM, P5_0_SCB5_UART_RX)
Cy_GPIO_SetDrivemode(UART_PORT, UART_RX_NUM, CY_GPIO_DM_HIGHZ)
For transmit data:
(void) Cy_SCB_UART_Transmit(SCB5, txBuffer, sizeof(txBuffer) and &uartContext)
For enable Interrupt:
(void) Cy_SysInt_Init(&uartIntrConfig, &UART_Isr) and NVIC_EnableIRQ(UART_INTR_NUM)
For other API's I referred https://infineon.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__scb__uart.html . Can anyone suggest why in FreeRTOS the same code I implemented without FreeRTOS is not working and does I have to include any PDL API for interrupt in FreeRTOS?
Show LessHi all,
I want to use freeRTOS in both cores but it uses the HAL. The PSoC™ 6 MCU: Dual-CPU empty application template says:
The Infineon HAL is not yet designed to run simultaneously on CM0+ and CM4 CPU. Because the proj_cm4 already uses HAL, proj_cm0p should only use PDL APIs.
Is this a problem if using Local git where each core gets a different copy of the HAL? if so, when will this issue be resolved.
Thanks
Show LessHello I designed in the psoc 5 part cy8c5468 QFN68 a few years ago now unavailable. So we bought a batch of a new psco 6 parts to maybe (hopefully replace it) CY8C6144LQI-S4F92. The problem is when I load up my project psoc creator 4.4 the new part is not listed in the device selector list? So I am unable to use it since I can't compile it. How can I get the part on the device list? Thanks.
Show LessAfter updating my project I cannot debug or program it anymore. My project was single core, I updated it to dual core and now the launches on quick panel are not working anymore.
I tried to re-generate the launches, erase all ".project" and ".cproject" (root, CM0 and CM4) and create again using "make eclipse" but nothing worked.
It shows this error:
This the MTB version MTB 3.0.0 build 2749
the command "make program" works, so I believe the issue is on Eclipse IDE.
thank you ,
Magnus
Show LessI have a project using a CY8C6x4 processor (CY8C6247FDI-D32). We have a requirement to service an interrupt on the M4 core at a very high rate (~ every 640us). We also have a requirement to write to flash memory using the M0 core while this interrupt is running. The M0 and M4 cores are running from flash in sector U1 (0x10040000) and the flash being written is U3 (0x100C0000). Below are a bunch of questions related to writing to flash using "partial blocking" methods.
Looking at the PSoC Peripheral Driver Library Flash Section (link) you can use partial blocking methods to try to keep the "non-flashing" core running while doing a flash erase and a flash write. The documentation has Figure 1 which shows some general timing for the StartErase() + StartProgram() method and the StartWrite() method. I have tried both and it looks like both processors get "locked" for a period of time.
Figure 1 has a Legend that shows "Available to read from flash", "Busy with SRM code (CM0+)", and "Blocking-out SRAM". I can figure out what (and see from my traces) what the first two mean. What I don't understand is what does "Blocking-out in SRAM" mean? Does this mean the processor can't execute from SRAM? Also what are the implications of this time period?
I'm trying to get something useful done on the M4 during the "Blocking-out in SRAM" period. From what I can see from traces I have collected is that there isn't much the M4 can do while the M0 is "starting the erase" and "starting the program". The code that I'm running is not getting interrupts during this period. So are both processors blocking in an NMI interrupt? Are interrupts disabled on both processors?
I understand that the M0 is tied up working with SROM and IPC during these times. I also understand that at least on the M0 a critical section cannot be entered. Is that true for the M4 as well? It the M4 locked up on IPC during these times as well?
I'm wondering if I can execute SRAM code on the M4 during this "Blocking-out in SRAM", but it isn't clear to me what blocking-out means. Also I'm not sure why I can't use Flash during this time since the sectors I'm using should be isolated. I have dug into the CY code that is interfacing with the SROM/IPC and it is running in SRAM (so that it is not using the flash or the flash cache).
Any help on this would be greatly appreciated and I suspect others would like to have a better understanding of what is going on while the SROM code is executing.
Best Regards,
Lenny