Trying to send a GATT notification with a payload of ~256 bytes between two BLE devices at 2Mbps. If the devices are at a distance where the initial attempt to send the notification fails (for example, if the frame check sequence is ``bad" as indicated by a sniffer), should a packet sniffer show attempts to retransmit the notification occurring with each successive connection event until transmission succeeds (i.e. frame check sequence ``good")? Is there any situation in which retransmission of a failed (i.e. unacknowledged) GATT notification does not occur during the very next device connection event (connection interval currently set to ~25ms), and if so, is there any firmware setting to control this time to retransmit?Show Less
I'm hoping somebody could please explain the pros and cons of running the PSOC 6 BLE stack on CM0 instead of CM4 like all sample code I've seen demonstrates. First of all, is running it on CM0 even possible? It seems to me that the BLE stack is a low load software module that should work equally well on either core. I would love it if somebody could point me to any appropriate (and current!) app notes and/or example projects.
I'm providing BLE programming expertise to a customer. I have only a few months of experience using the PSOC 6 BLE module so the core selection tradeoff is new to me.
Thanks - JJSShow Less
In one project,I found tow same named fuction in the same .c file,how the modustollbox design which funtion to be build?
We have a CY8CKIT-064S0S2-4343W kit that we're trying to get up and running with the demonstration code that is generated from AWS. I'm following the getting started guide located here https://docs.aws.amazon.com/freertos/latest/userguide/getting_started_cypress_psoc64.html and have successfully done everything up to the point of getting working code.
I've managed to build and flash the provided demo application, and the board successfully boots but then halts shortly after with "ERROR: stack overflow" — the attached screenshot shows what is happening. This happened with no WiFi credentials set, I then tried to set WiFi credentials and the error still happened.
Any help in resolving this issue would be appreciated!Show Less
I am interested in designing a solution for measuring TDS (Total Dissolved Solids) in water and sending the data over the 12V power line to the receiving end where the data is displayed.
I remember using a PSoC for power line communication a long time ago before the PSoC PLC version was released.
If I want to combine using a PSoC for both TDS and PLC, which PSoC do you recommend?
The CY8CPROTO-063-BLE board is being used with hibernate and periodic alarms to save system power. The RTC is producing the expected alarms and the hibernate control is working properly. There is an external PMIC with an enable input to turn it on and off to generate the 3.3V input for the VDD . A supercap is attached to VBACKUP and R29 is removed on the board. When the unit is also powered from the KipProg3 adapter (via VTARG) it works as intended, hibernating and waking up periodically. However, When the KitProg3 is unpowered and the external power is only applied into the PMIC, it never gets out of hibernation.
The problem is that pin P0.5 is not being controlled by the hibernate logic as needed. The PMIC enable (active high) is pulled high by a weak pull-up resistor for when the PSoC 6 is not yet powered or not yet in control ( P0.5 assumed high impedance). When hibernate mode is started, P0.5 should be pulled low by the PmicEnableOutput and when it goes out of hibernate, it should be pulled high to turn the external PMIC on. This is not happening.
In response to the forum question "PSoC 6 PMIC Control deep sleep best practise", GaneshD_41 replied suggesting control that is built into the following code:
Cy_SysPm_SetHibWakeupSource( CY_SYSPM_HIBALARM // Wake-up source for RTC alarm
| CY_SYSPM_HIBPIN1_LOW // Wake-up source for Pin1 input low
Cy_SysPm_PmicUnlock(); // Unlock in case locked
//NU Cy_SysPm_PmicEnable(); // enable Pmic control
Cy_SysPm_PmicEnableOutput(); // enable P0.5 output control
Cy_SysPm_PmicLock(); // Lock again but why?
// Configure the PMIC controller output pin to be active logic low
// after the PMIC is disabled.
// Note: I do not understand the above comment
Cy_GPIO_SetDrivemode(P0_5_PORT, P0_5_PIN, CY_GPIO_DM_STRONG_IN_OFF); // What does this do?
Cy_GPIO_Clr(P0_5_PORT, P0_5_PIN); // What does this do?
if ( Cy_SysPm_PmicIsOutputEnabled() ) // It was just enabled above; so why check?
Cy_SysPm_PmicDisable(CY_SYSPM_PMIC_POLARITY_LOW); // what does this do?
// Prepare the device for system Hibernate
if ( Cy_SysPm_SystemEnterHibernate() != CY_SYSPM_SUCCESS )
/* System did not enter Hibernate mode because a registered
* Hibernate "check ready" callback returned a "not success" status
printf(" Hibernate failed\r\n\n");
Cy_SysLib_Delay(1000); // wait for output
The above code was put into the project; yet P0.5 still does not have any output; it always stays low.
Are there any suggestions as to properly controlling the P0.5 pin while going into and out of hibernation?Show Less
I am very new to the world of BTLE, but have a large background in electrochemistry. I am currently curious about trying to power the PSOC6 purely off electrochemical reactions (glucose and glucose oxidase). I wold like to measure the potetnial over a resitior, or charge pump, or anyhting that would minimize power, and simply send that raw value via bluetooth in the lowest energy consuming form possible. I apologies if this is to vauge. If there is a simpler solution then the PSOC6 (from what i hear this is a very complex chip) i am all ears!
David ProbstShow Less
I want to know the CPU current of the PSoC61 series, but the datasheet only has information about dual-core device (why?).
Please tell me the CPU current specifications for single-core products.
I am currently using a psoc CY8C6347BZI-BLD53 to do some very high speed SPI transfers at 25MHz and have come across some interesting behavior of the SPI FIFO.
Initially I was using the Cy_SCB_SPI_Write() to fill the FIFO to 64 with uint16_t values that is triggered when the FIFO reached a value of 8. Upon further investigation with an oscilloscope there was some delay between transfers (~570ns) and a larger delay (~972ns) between them when writing to the FIFO during an interrupt using that api.
The delay between each message becomes one clock cycle consistently when using Cy_SCB_WriteTxFifo() even while writing to the FIFO which solves my timing critical problem. However, I now begin to receive the interrupt after ~30 values being transferred, which means the FIFO isn't being fully filled to the value of 64 (i'm guessing ~38) . I found that if I add a delay of ~20 cycles after each call of Cy_SCB_WriteTxFifo() the right number of data (54) can be seen transferring on the oscilloscope before the next interrupt occurs.
I am reaching out for some help with trying to eliminate the added delay cycles after each Cy_SCB_WriteTxFifo, or at least to understand the root cause of why it work when they're there. I have looked into the TRM for the architecture, but they do not go into detail about FIFO operation. I don't have a usb right now so I can't post images from my oscilloscope but if you need them to understand I should have one by this Monday.
Your help is greatly appreciated!Show Less
Why the device nane , the defined symbols field of C/C++ compiler can't change synchronously When I change the devices from CY8C624ABZI-D44 to CY8C624AAZI-S2D44? It will lead to a Mistake to inclde the header file of cy8c624abzi_d44.h!!!