PSoC™ 6 Forum Discussions

Is there a way to optimize the size of the application by removing any unused libraries or other ways? The -Os option has already been tried; it helps but not in any significant way. If there are other ways to manually remove any unused libraries/source code? We are willing to try anything.

Greg

Which are the least expensive uC's with 16-bit or better ADC, I2S out, and FPU?

(I'm not asking about PSoC6, but this forum required me to pick something)

Hello community!
I have a project that reads ML8511 + BME280 + PSoC 6 BLE sensors
Previously when I only had the ML8511 sensor, I could connect BLE and send data via Android APP!
But after adding the BME280 sensor to the project, the BLE connection error occurred!
I think the problem is with my code!
I have attached my project! Hope everyone can take a look and help me revise this project!
Thank!.

Hi, I am developing firmware using PSoC6, and using Em_EEPROM.

In the example project, below is how the error is processed:

eepromReturnValue = Em_EEPROM_Read(LOGICAL_EEPROM_START, eepromArray, LOGICAL_EEPROM_SIZE);
if(eepromReturnValue != CY_EM_EEPROM_SUCCESS)
{
HandleError();
}

void HandleError(void)
{
UART_PutString("Error! \n\r");
/* Disable all interrupts. */
__disable_irq();

/* Infinite loop. */
while(1u) {}
}

I am wondering if it is possible to reset the Em_EEPROM for error handling. Such as set all the values in the Em_EEPROM to 0.

Looking forward to your reply.

Hello,

I have been using Zephyrwith the  cy8cproto-063-ble module, and I need to implement a high-speed SPI driver. Unfortunately, the Zephyr driver overhead gives each transfer a ~25us extra delay to every SPI transfer, which is too much for our application. 

I figured using HAL would be faster, but I can't find any examples of how to pull in HAL from Infineon devices. I've set the flag `CONFIG_SPI_INFINEON_CAT1=y`in my prf.conf and used `#include <cyhal.h>` and `#include <cy_scb_spi.h>`, but  linking fails with messages such as `undefined reference to cyhal_spi_transfer`.

I would appreciate any help !

Best

I have a custom BSP based on a Cy8C6137BZI-F14 running on the CM4 (we're not doing anything with the CM0). In this project, the CLK_FAST is initialized to 8 MHz, CLK_HF0 is 96 MHz and sourced from the FLL (also 96 MHz) which is sourced from the ECO at 16 MHz.  We do change the FAST clock around between 8 MHz / 24 MHz / 48 MHz and are making the appropriate calls to Cy_SysLib_SetWaitStates() and SystemCoreClockUpdate() upon doing so. Our project is using FreeRTOS and in the vApplicationSleep(), before we enter Deep Sleep via Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT), we disable the LVD. Upon exiting Deep Sleep, we re-enable the LVD. Per the Infineon PDL manual and TRM, it is required to have a 20uS minimum delay to avoid false interrupts (learned from experience). In our development, 20 uS did not seem to be sufficient, so ended up increasing it to 35 uS.

I have just encountered an issue with the false LVD trip again upon coming out of Deep Sleep, so have been digging into this again. This issue is only observed when the debugger is not attached (typically running a Custom config with optimization level set to -O1). I have increased the delay to 50uS and still getting the reset. Trying to figure out why, I added a GPIO toggling low prior to Cy_SysLib_DelayUs(50) and return the GPIO high afterwards. And to my surprise, the delay is only taking 24uS! I tried increasing the delay to 75 uS and on my logic analyzer, it is taking 32.5 uS! After digging around in manuals again, I was not coming up with any reasoning, I tried setting the PSoC SystemCoreClock variable to volatile with no change in behavior. Out of curiosity, I then called SystemCoreClockUpdate() immediately upon exiting Deep Sleep, so before the LVD is enabled and Cy_SysLib_DelayUs() being called. Low and behold, the delay is now as it is supposed to be!

I've been poking around on the community but not finding any direct examples of others having the issue. https://community.infineon.com/t5/PSoC-6/Frequency-Calculation-bug-when-using-ExtClk-but-ok-with-IMO/td-p/390114 seems similar, but not quite. Is it stated somewhere that SystemCoreClockUpdate() is supposed to be called upon exiting Deep Sleep? The manual for Cy_SysPm_CpuEnterDeepSleep() states, "This function changes the slow and fast clock dividers right before entering into system Deep Sleep and restores these dividers after wakeup" so the clocks are returned to what we expect them to be, but is there possibly a bug that is not recalculating the variables used in the system delay functions?

Cheers

Hello community
I'm a beginner
Currently I have a project to read BME280 sensor on PSoC 6 using PSoC Creator 4.4 (BLE_Sensor_Notify.cydsn.zip)
I'm trying to edit from another project written on PSoC 5. (BME280.cydsn.zip)
But I'm having some problems and I can't read the BME280 sensor as expected!
Can you help me find the error and fix it for me?
Thank you everybody!

Hello,

After a long absense from Cypress technology,  I have returned to investigate replacing the PSoC 3 we have used in our ham radio products for years with a PSoC 6.   I have obtained the CY8PROTO-063-BLE prototype kit as a start of my investigations.

Using PSoC Creator 4.2 the first snag I hit was the CYBLE-416054-02 was not in the device selector.   An internet search revealed this was an easy fix by going to tools-> find new devices.   OK,  good now I have the device.  

I am following this guide:  https://www.infineon.com/dgdl/Infineon-CY8CPROTO-063-BLE_PSoC_6_BLE_Prototyping_Board_Guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812 to get my feet wet with programming the PSoC 6.   But of course the program will not build with the following error:

What does this error mean and how do I fix it?

Regards,

Ron

Dear Receiver,

Could you please help me to check the schematic in the attached file ?!

It's a minimum system demo kit.

Do you have any comment about this kit ?!

Thank you so much.